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MSP432P401R: msp432 example eUSCI code directly contradicts the TRM

Eric Decker
Expert 1420 points

Part Number: MSP432P401R

greetings,

I've noticed the following line in MSP432Ware_3_50_00_02/examples/devices/MSP432P4xx/MSP432P401x_Code_Examples/C/msp432p401x_euscib0_spi_09/msp432p401x_euscib0_spi_09.c

in particular the line setting BRW and the comment saying   that the bitclock to f_brclk/UCBRx+1.

This directly contradicts pg 760, section 23.3.6 of the TRM, slau356e which clearly states that F_bitclock = F_brclk/UCBRx

which is how I remember programming these buggers.   I assume that the TRM is correct  YES?

Could I suggest that some one go through the examples and fix this?   It sows confusion.

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