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MSP430G2553: MSP430 / MSP432 - external start trigger/interrupt, precise time delay generation with 50 ns resolution?

Timo1
Prodigy 40 points
Part Number: MSP430G2553

Dear all,

I have used a simple MSP430G2553 for interfacing an ASIC in a lab prototype. Now I would like to replace an external FPGA that is used to generate precise delays on a digital signal with a MCU. The application is the following:

0) A main program runs on the MCU.

1) An external asynchronous digital trigger arrives (digital pulse) from the ASIC trigger line,

2) the MCU / FPGA registers the trigger and causes an interrupt,

3) the MCU / FPGA issues a digital signal (high, default state: low) to another ASIC line (Sample-and-Hold - S/H) after a programmable time t (t = {500 - 1000} ns) in 50 ns or smaller time steps.

4) After the readout system has obtained the data the digital S/H signal is reset. The main program continues.

For now a FPGA has been used to carry out the delay task. However, I wish to move to a MCU instead for a simpler design. 

Question: Is it possible to use a TI MSP430 / MSP432 MCU to achieve the above aim? The internal clock of a MSP430 is on the order of 16 MHz (t=62.5 ns). I suppose it takes a couple of instructions to carry out the above tasks. What about time jitter?

I was looking into programmable delay line ICs but these appear to become a rarity (e.g. AD9501, Data Delay Devices ICs, some Maxim ICs). Alternatively, a CPLD but I would prefer an MCU-based solution. I have read about high-speed TIMER_D peripheral on TI MSP430x5xx and MSP430x6xx family devices. However, I am not getting my head around as to how a TIMER_D peripheral can help me achieve my aim. Any thoughts?

Thanks!

  • 0
    TI__Genius 14875 points
    Timo,
    I should mention that there are faster MSP's (25MHz) and MSP432 is 48MHz.
    Perhaps I am missing something, but could you not use a GPIO interrupt for step 1 to start a timer and set a timer interrupt to issue the digital signal in step 3? The same interrupt could also change the low to high threshold for the GPIO interrupt to read when transfer is complete.

    How is the data being transferred?
  • 0
    Guru 12050 points

    Single core MCU's with interrupt-systems are not good at precise software timings.

    Instead of bunch of parts "glued" together, why not go with a single "8-core" Parallax Propeller P8X32A

    You get exact 10ns steps with a 6.25Mhz Crystal.

  • 0 in reply to Tony Philipsson
    TI__Genius 14875 points

    Timo,

    Have you solved this issue? If not, can you give us an update so we may continue to help?

  • 0 in reply to Cameron LaFollette
    Prodigy 40 points

    Dear Cameron and Tony,

    Thanks for the input! Regarding the Parallax Propeller, interesting device, however, I do not see it replace the MSP430 for all other tasks that are necessary to operate my instrument (hardware peripherals). I also looked at XMOS MCUs and Adapteva Epiphany multi-core co-processors with the same outcome. If the MSP43x approach does not work out I will try them out. 

    Regarding the MSP43x approach, indeed I think even the 16 MHz MSP430 (t_clk = 62.5 ns) will be good enough given the time jitter is small (< 50 ns). I also need to measure the minimum time delay between external interrupt and the ISR to run. The question is as to how deterministic one can get the time delay between the IC trigger and S/H signal to be applied on the MCU output pin. I did not have time over the holidays but will try this out in the next few days and get back to you.

    The instrument is a prototype for a CubeSat payload hence it would be best to be able to use a MCU that could potentially be replaced with a rad-hard part in the end. FRAM-based MSP430 are also interesting for this application when going the COTS pathway. In the end the S/H signal stays high for as long as it takes to read out an ADC value (potentially the built-in MSP430 ADC) and clocking through a few analogue shift registers on the external IC i.e. applying a number of clocks on a IC pin. When the readout is completed the S/H signal is reset (low).

    Thanks for your help!

    Timo

  • 0 in reply to Timo1
    Guru 12050 points

    If you need ns delays, simply use R/C going to AND gate (or a OR/XOR that could work for you)

    If gate have a precise schmitt trigger voltage you will know when it will fire. Example 3.3V in, 2V trigger, 0.011K ohm, 0.1uF Cap = 1uS delay

    ladyada.net/.../rccalc.html

  • 0 in reply to Timo1
    Guru 46710 points

    Timo1 said:
    Regarding the MSP43x approach, indeed I think even the 16 MHz MSP430 (t_clk = 62.5 ns) will be good enough given the time jitter is small (< 50 ns).

    Worst case input and resulting output jitter is one clock period of the timer. Do not even think of involving CPU because (im)precision could reach tens of CPU clock cycles even in case of hand-optimized assebly code. I know how to do such programmable pulse delay with stm32 timers, but I am not sure about msp430. Perhaps other TI microcontrollers (like Tiva or Piccolo) have proper timers, but then you have to investigate.

  • 0 in reply to Timo1
    Guru 12050 points

    Not to put TI down, but no msp430 can do the job.
    1: Parallax Prop, you could put one cog in waitpin sleep, wakeup up ~10nS error,
    each nop take exactly 40nS. or use waitcnt after wakeup for 10nS ticks but minimum is 5 ticks.
    2: Cypress Psoc5 UDB, should be able to pin-in to pin-out with a programmable delay in hardware.

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