Hello ....,
I have used an example fet140_i2c_06.s43 MSP430F169 Master and fet140_i2c_07.s43 MSP430F169 Slave to test I2C Transfer.
At my Oszilloscope I can see, the Master send the Slave-Adress but the Slave set not the acknoweledge Bit at the right time. What is the Reason for this?
further details:
- After the start, the SDA line is high at the 9th Clk-cycle (ACKN)
- The high-Periode is available 5.2us.
- then the slave set the SDA low. (a delayed ACKN?)
Is this a timing problem?
I am grateful for help.
regards Jurgen Rieger
