Part Number: MSP432P401R
Hi.
i am trying to operate SPI_B2 (P3.5-3.7) through DMA channels 6,7 but it simply doesn't work i'm initiating the SPI_B2 and testing it without the DMA channels and it works, but when i use the DMA channel, the initiation of the channels are correct and the control word in the DMA table is correct also, but the DMA does not move and the control word shows it does not decrements the number of bytes left to transmit.
the SPI2 is initiated correctly, since i can manually write to the UCBTXBUF of EUSCI_B2 and see the byte and the clock with logic analyzer on P3.5-P3.6.
i'm attaching the relevant part of the code (only the TX DMA):
DMA_data_struct DMAcontrolTable[16]; //8 DMA ch * 2 (ALT ch) = 16*4*4 bytes
#pragma DATA_ALIGN(DMAcontrolTable, 256)
UC TestArray[10] = {1,2,3,4,5,6,7,8,9,10};
// SET the SPI2 peripheral
//--------------------------------=
MAP_GPIO_setAsPeripheralModuleFunctionOutputPin(GPIO_PORT_P3, GPIO_PIN5 | GPIO_PIN6 | GPIO_PIN7, GPIO_PRIMARY_MODULE_FUNCTION);
EUSCI_B2->CTLW0 |= EUSCI_B_CTLW0_SWRST; // Put eUSCI state machine in reset
EUSCI_B2->CTLW0 = EUSCI_B_CTLW0_SWRST | // Remain eUSCI state machine in reset
EUSCI_B_CTLW0_CKPL | // Set clock polarity high, CKPH=0. data sampled on the rising edge of the clock.
EUSCI_B_CTLW0_MSB | // MSB first, 8bit
EUSCI_B_CTLW0_MST | // Set as SPI master
EUSCI_B_CTLW0_MODE_0 | // 3-wire mode 00
EUSCI_B_CTLW0_SYNC | // Set as synchronous mode
EUSCI_B_CTLW0_SSEL__SMCLK | // use SMCLK
EUSCI_B_CTLW0_STEM ; // ignored in 3-wire mode, in 4 wire mode activates Slave enable signal.
EUSCI_B2->BRW = (US)(SMClock / 1000000); // fBitClock = fBRCLK/(UCBRx+1).
EUSCI_B2->CTLW0 &= ~EUSCI_B_CTLW0_SWRST; // Initialize USCI state machine
MAP_SPI_enableModule(EUSCI_B2_BASE);
/* Configuring DMA module */
//--------------------------------------------------
MAP_DMA_enableModule();
MAP_DMA_setControlBase(DMAcontrolTable);
// Assigning Channel 6 to EUSCIB2TX
//----------------------------------------------------------------
MAP_DMA_assignChannel(DMA_CH6_EUSCIB2TX1);
/* Setting up Buffer for primary */
MAP_DMA_setChannelControl(DMA_CH6_EUSCIB2TX1 | UDMA_PRI_SELECT, UDMA_SIZE_8 | UDMA_SRC_INC_8 | UDMA_DST_INC_NONE | UDMA_ARB_1);
/* Setting up Buffer for alternate */
MAP_DMA_setChannelControl(DMA_CH6_EUSCIB2TX1 | UDMA_ALT_SELECT, UDMA_SIZE_8 | UDMA_SRC_INC_8 | UDMA_DST_INC_NONE | UDMA_ARB_1);
// Clear the high priority bit for this channel.
// DMA_Control->PRIOCLR = 1 << 6; // has no effect
/* Assigning interrupt to DMA channel */
MAP_DMA_assignInterrupt(DMA_INT0, DMA_CHANNEL_6); // assign to the general DMA0
/* Enable intrrupts for DMA channels */
// NVIC->ISER[1] = 1 << ((DMA_INT0_IRQn-32) & 31);
MAP_Interrupt_enableInterrupt(DMA_INT0);
// set a 6 byte length transfer
//---------------------------------------
MAP_DMA_setChannelTransfer(UDMA_PRI_SELECT | DMA_CH6_EUSCIB2TX1 , UDMA_MODE_BASIC, &TestArray[0],
(void*) MAP_SPI_getTransmitBufferAddressForDMA(EUSCI_B2_BASE), 6);
/* Enable DMA channel */
MAP_DMA_enableChannel(DMA_CHANNEL_6);
/* Now that the DMA is primed and setup, enabling the channels. The EUSCI
* hardware should take over and transfer/receive all bytes */
