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MSP430FR58891: Oscillator Fault

Part Number: MSP430FR58891
Other Parts Discussed in Thread: MSP430F2272, MSP430FR5969

I am working with a new board with a msp430fr58891. I keep getting a oscillator fault. I would like to have someone double check my code before I ask the PCB designer to move the crystal closer to the chip. The LFX pins are floating and we have asked they be terminated in the next version. Section 4.6 gives advise on unused pins but give no advise on unused LFX pins, should that be tied to Vss?

So is there anything I am doing wrong in my code that would cause a OSC Fault in SFRIFG1_bit.OFIFG?

I have made multiple changes trying to correct but nothing helps.

I switched to the MCLK and SMCLK to the internal DCO running at 4 and 16MHz  but that did not help.

I increased the HFDRIVE but again nothing.

I have a LaunchPad Demo board with 5969 but I have the same problem with the DCO (the LaunchPad does not have a crystal installed for HFX (XT2)).

static void Start_XT1( void ) {
uint16_t i;
uint16_t status;

CSCTL0 = 0xA500; //PWD GAA
// CSCTL1 = 0x0006; //DC0 Range Sel: 4MHz GAA
CSCTL1 = 0x0048; //DC0 Range Sel: 16MHz GAA
CSCTL2 = 0x0055; //ACLK=LFXT(or VLOCLK), SMCLK=HFXT(or DCOCLK), MCLK=HFXT(or DCOCLK) GAA
// CSCTL2 = 0x0033; //ACLK=LFXT(or VLOCLK), SMCLK=DCOCLK, MCLK=DCOCLK GAA
// CSCTL3 = 0x0000; //ACLKDIV=1, SMCLKDIV=1, MCLKDIV=1 GAA
CSCTL3 = 0x0011; //ACLKDIV=1, SMCLKDIV=2, MCLKDIV=2 GAA
// CSCTL4 = 0x0000; //HFXT,LFXT: HFXTDRIVE= 00, HFFREQ= 00 0-4MHz 5969 GAA
// CSCTL4 = 0x0800; //HFXT,LFXT: HFXTDRIVE= 00, HFFREQ= 01 8-16MHz GAA
// CSCTL4 = 0x4800; //HFXT,LFXT: HFXTDRIVE= 01, HFFREQ= 01 8-16MHz GAA
// CSCTL4 = 0x8800; //HFXT,LFXT: HFXTDRIVE= 10, HFFREQ= 01 8-16MHz GAA
CSCTL4 = 0xC800; //HFXT,LFXT: HFXTDRIVE= 11, HFFREQ= 01 8-16MHz GAA
CSCTL5 = 0x0080; //LFXT&HFXT FaultCntrEnable: HFXT Fault Flags Enabled
// CSCTL6 = 0x0000; //MODCLK,SMCLK,MCLK,ACLK request enable: all disabled
CSCTL6 = 0x000F; //MODCLK,SMCLK,MCLK,ACLK request enable: all enabled

PJSEL1_bit.PJSEL1_6 =0; // msp430fr58891 64-pin: HFXOUT PJ.7 pin54 HFXIN PJ.6 pin55
PJSEL0_bit.PJSEL0_6 =1;

/do {
SFRIFG1_bit.OFIFG = 0; // Clear the OSC Fault Flag IFG1_bit.OFIFG = 0;
for(i = 0; i < 1000; ++i) { dummy++;};
} while( SFRIFG1_bit.OFIFG ); // Don't continue if still set IFG1_bit.OFIFG

status =1;

}

  • When configured as LFXIN/OUT, the LFX pins must not be unused (see footnote 1 of table 1-4).

    The OFIFG flag just reports that at least one of LFXTOFFG or HFXTOFFG is set. You have to clear those flags, too (and ensure that you do not try to use HFXT or LFXT when there is nothing connected).

    All the CSCTL register values are wrong. (This is what I assume when I see somebody using magic numbers instead of proper symbols.)

  • Thank you.  We are not using LFX and have left the pins in the default state as GPIO.

    1.2.1 Device Initial Conditions After System Reset
    After a BOR, the initial device conditions are:
    • The RST/NMI pin is configured in the reset mode. See Section 1.7 for details on configuring the
    RST/NMI pin.
    • I/O pins are switched to input mode as described in the Digital I/O chapter.

    1.6 Connection of Unused Pins
    The correct termination of all unused pins is listed in Table 1-4. p. 54

    Px.0 to Px.7 Open Switched to port function, output direction (PxDIR.n = 1)

    12.3.1 Configuration After Reset
    After a BOR reset, all port pins are high-impedance with Schmitt triggers and their module functions
    disabled to prevent any cross currents. The application must initialize all port pins including unused ones
    (Section 12.3.2) as input high impedance, input with pulldown, input with pullup, output high, or output low
    according to the application needs by configuring PxDIR, PxREN, PxOUT, and PxIES accordingly.

    yeah that's not confusing....

    HFXTOFFG and LFXTOFFG are cleared in CSCTL5 at the end of my initialization routine. I so periodically test SFRIFG1 to see if  OFIFG flag is set and I clear it. I'll start clearing HFXTOFFG also.

    I used the msp430fr58xx Family Guide manual to determine the settings of the CSCTLs, if they are wrong then TI needs to update the manual. Hopefully someone else will see this and review my settings against the manual.

  • yeah that's not confusing....

    The three sections you quoted are correct and consistent. What is the problem?

    I used the msp430fr58xx Family Guide manual to determine the settings of the CSCTLs

    Have a look into the msp430‍fr58891.h header file, for example:

    ...
    /* CSCTL2 Control Bits */
    ...
    #define SELM__LFXTCLK       (0x0000)   /* MCLK Source Select LFXTCLK */
    #define SELM__VLOCLK        (0x0001)   /* MCLK Source Select VLOCLK */
    #define SELM__LFMODCLK      (0x0002)   /* MCLK Source Select LFMODOSC */
    #define SELM__LFMODOSC      (0x0002)   /* MCLK Source Select LFMODOSC (legacy) */
    #define SELM__DCOCLK        (0x0003)   /* MCLK Source Select DCOCLK */
    #define SELM__MODCLK        (0x0004)   /* MCLK Source Select MODOSC */
    #define SELM__MODOSC        (0x0004)   /* MCLK Source Select MODOSC (legacy) */
    #define SELM__HFXTCLK       (0x0005)   /* MCLK Source Select HFXTCLK */
    ...
    #define SELS__LFXTCLK       (0x0000)   /* SMCLK Source Select LFXTCLK */
    #define SELS__VLOCLK        (0x0010)   /* SMCLK Source Select VLOCLK */
    #define SELS__LFMODCLK      (0x0020)   /* SMCLK Source Select LFMODOSC */
    #define SELS__LFMODOSC      (0x0020)   /* SMCLK Source Select LFMODOSC (legacy) */
    #define SELS__DCOCLK        (0x0030)   /* SMCLK Source Select DCOCLK */
    #define SELS__MODCLK        (0x0040)   /* SMCLK Source Select MODOSC */
    #define SELS__MODOSC        (0x0040)   /* SMCLK Source Select MODOSC (legacy) */
    #define SELS__HFXTCLK       (0x0050)   /* SMCLK Source Select HFXTCLK */
    ...
    
    #define SELA__LFXTCLK       (0x0000)   /* ACLK Source Select LFXTCLK */
    #define SELA__VLOCLK        (0x0100)   /* ACLK Source Select VLOCLK */
    #define SELA__LFMODCLK      (0x0200)   /* ACLK Source Select LFMODOSC */
    #define SELA__LFMODOSC      (0x0200)   /* ACLK Source Select LFMODOSC (legacy) */
    ...

    (But there also are lots of not-so-useful symbols for backwards compatibility.)

  • Clemens, Please don't reply to any more of my post.
  • Still hoping that someone will review my clock initialization software and give some advice. Sorry that I did not use the defined macros, this is my first msp430. I inherited this design from a previous vendor and the customer wants it ported from the msp430f2272 to the 58891. The code did not produce an OSC Fault while running on the 2272. I had one comment to clear the HFXTOFFG in CSCTL5. I do that at initialization but now also clear it in my main loop when I find that SFRIFG1_bit.OFIFG == 1. This does not correct the problem.

    if ( SFRIFG1_bit.OFIFG == 1) {
    SFRIFG1_bit.OFIFG =0;
    CSCTL5_bit.HFXTOFFG = 0; // Clear the HFXT OSC Fault Flag
    CSCTL5_bit.LFXTOFFG = 0; // Clear the LFXT OSC Fault Flag

    I have tried changing multiple things, one of which was setting MCLK and SMCLK to DCO. Certainly that should not produce a OSC Fault but it does? I also have a LaunchPad demo board with the msp430fr5969 and have the same results there???? Other than that my code runs fine, still really hate the OSC Fault.

  • Okay, LFXT is setting the fault. I have the LFXT osc fault turned off so I didn't think it could set the fault but it does. As I don't use LFXT I would like to ignore for now. But I also found this is the forum:

    TI E2E Forum: Oscillator fault flag never clears on 430F5659

    • TI should be more explicit about this in the userguides. It's really hard to find, and even then not very clear.

    The issue seems to be associated with BAKDIS
    After a POR the oscillator is powered from Vbat and XT1 operation is not modifiable.
    BAKDIS changes the power to VCC and allows changing the module's operation.

    After testing BAKCTL |= BAKDIS seems to be enough to fix the issue, but forums and application notes suggest clearing LOCKBAK as well.

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