MSP430FR4133: MSP430FR4133 MCLK Default

Part Number: MSP430FR4133

I am using a MSP4320FR4133 and not setting the MCLK.  But I do set the SMCLK at 1 MHZ for my SPI:

  WDTCTL = WDTPW | WDTHOLD;                 // Stop watchdog timer

    configRTCTimer();

    P5SEL0 |= BIT0 | BIT1 | BIT2 | BIT3;      // set 4-SPI pin as second function

    UCB0CTLW0 |= UCSWRST;                     // **Put state machine in reset**
                                            // 4-pin, 8-bit SPI master
    UCB0CTLW0 |= UCMST|UCSYNC  | UCMSB|UCMODE_2|UCSTEM;
                                                  // Clock polarity high, MSB
        UCB0CTLW0 |= UCSSEL__SMCLK;              // SMCLK
        UCB0BR0 = 0x01;                           // /1,fBitClock = fBRCLK/(UCBRx+1) Clock at 1MHZ.
        UCB0BR1 = 0;                              //
       // UCB0MCTLW = 0;                            // No modulation
        UCB0CTLW0 &= ~UCSWRST;                    // **Initialize USCI state machine**
        UCB0IE |= UCRXIE;                         // Enable USCI_A0 RX interrupt


    PM5CTL0 &= ~LOCKLPM5;                     // Disable the GPIO power-on default high-impedance mode

Does this a an effect on my MCLK?  What would the MCLK frequency be?

Thanks