MSP432P401R: ClockSystem example bundled with MSP432 GCC does not work

Dan Cermak

Part Number: MSP432P401R
Other Parts Discussed in Thread: MSP432WARE

Hi everyone,

I have tried using the clock system example (msp432_gcc/examples/MSP432P401/msp432p401_cs/) which is bundled with GCC for the MSP432 (I wanted to try the HFXT) and have found some serious issues.

The issue is the setting of multiple bytes several registers, which is implemented wrongly, e.g. the setting of flash wait states (file msp432p401_cs.c, line 112):

FLCTL->BANK0_RDCTL = FLCTL->BANK0_RDCTL & ~(FLCTL_BANK0_RDCTL_WAIT_MASK | FLCTL_BANK0_RDCTL_WAIT_2);

I guess that the idea was to zero out the bits belonging to the wail states and then set 2 wait states, but the brackets are wrong to achieve that.

This exact same error can be found three times in the file msp432p401_cs.c, on lines 112, 113 and 127 (the first to try to set the flash wait states and the third tries to source MCLK from HFXT):

    /* Step 2: Configure Flash wait-state to 2 for both banks 0 & 1 */
    FLCTL->BANK0_RDCTL = FLCTL->BANK0_RDCTL & ~(FLCTL_BANK0_RDCTL_WAIT_MASK | FLCTL_BANK0_RDCTL_WAIT_2); // line 112
    FLCTL->BANK1_RDCTL  = FLCTL->BANK0_RDCTL & ~(FLCTL_BANK1_RDCTL_WAIT_MASK  | FLCTL_BANK1_RDCTL_WAIT_2); // line 113

    // ...

    /* Select MCLK & HSMCLK = HFXT, no divider */
    CS->CTL1 = CS->CTL1 & (~(CS_CTL1_SELM_MASK | CS_CTL1_DIVM_MASK | CS_CTL1_SELS_MASK | CS_CTL1_DIVHS_MASK) | CS_CTL1_SELM__HFXTCLK | CS_CTL1_SELS__HFXTCLK); // line 127

Since the parts of the registers which have to be set are reset with zero, this can be fixed via:

    /* Step 2: Configure Flash wait-state to 2 for both banks 0 & 1 */
    FLCTL->BANK0_RDCTL |= FLCTL_BANK0_RDCTL_WAIT_2; // line 112
    FLCTL->BANK1_RDCTL  |= FLCTL_BANK1_RDCTL_WAIT_2; // line 113

    // ...

    /* Select MCLK & HSMCLK = HFXT, no divider */
    CS->CTL1 |= CS_CTL1_SELM__HFXTCLK | CS_CTL1_SELS__HFXTCLK; // line 127

With this everything should work.

No offense TI, but has actually someone tested this? The code lines further down in the file even expose the MCLK via P4.4, if someone connected a scope the error should have become apparent.

Please fix this upstream,

Dan

over 9 years ago

0 Bob Heilmaier over 9 years ago

TI__Prodigy 595 points

Hey Dan,

thanks for point that one out. I just checked that latest version of MSP432Ware 3_50_00_02 release and see that this has already been fixed.

Example msp432p401_cs_09 contians:

/* Step 2: Configure Flash wait-state to 1 for both banks 0 & 1 */
FLCTL->BANK0_RDCTL = (FLCTL->BANK0_RDCTL & ~(FLCTL_BANK0_RDCTL_WAIT_MASK)) |
            FLCTL_BANK0_RDCTL_WAIT_1; // line 112
FLCTL->BANK1_RDCTL = (FLCTL->BANK0_RDCTL & ~(FLCTL_BANK1_RDCTL_WAIT_MASK)) |
            FLCTL_BANK1_RDCTL_WAIT_1; // line 115

/* Select MCLK & HSMCLK = HFXT, no divider */
CS->CTL1 = CS->CTL1 & ~(CS_CTL1_SELM_MASK | CS_CTL1_DIVM_MASK | CS_CTL1_SELS_MASK | CS_CTL1_DIVHS_MASK) |
            CS_CTL1_SELM__HFXTCLK | CS_CTL1_SELS__HFXTCLK; //line 127

For the next MSP432 GCC Support Package release, the examples will be updated.

Thanks,

Bob Heilmaier