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MSP432P401R: Watchdog timer

Govind Gaundalkar
Prodigy 90 points

Part Number: MSP432P401R

Hi

I am trying to set the wqtchdog timer overflow as a soft reset.hence I am checking the RSTCTL_SOFTRESET_STAT_SRC1 register.If there is a 1 in bit position 1 it means the source of reset is watchdog soft reset.

But what I hv observed is thet even before the reset occurs the value in RSTCTL_SOFTRESET_STAT_SRC1 is a 1 indicating a rsest.I tried clearing it through the statement  RSTCTL->SOFTRESET_CLR = 2;but does not clear .How to clear the watchdog RSTCTL_SOFTRESET_STAT_SRC1 register bit 1.

void main(void)
{

WDTCTL = WDTPW | WDTHOLD; // Stop watchdog timer
rst = RSTCTL_SOFTRESET_STAT_SRC1;  //value here is 2
RSTCTL->SOFTRESET_CLR = 2;
rst = RSTCTL_SOFTRESET_STAT_SRC1; //value here should be 0 but appears as 2,whcih means SRC1 is not clearing
   if(rst == 2)

{ //if watchdog overflows this flag is set
  RSTCTL->SOFTRESET_CLR = 2;
  WATCHDOG_Reset_Indicator();
}

WATCHDOG_Init();

  • 0
    Intellectual 690 points
    You are not querying the contents of the SOFTRESET_STAT register, RSTCTL_SOFTRESET_STAT_SRC1 is a macro (defined in msp432p401r.h):
    #define RSTCTL_SOFTRESET_STAT_SRC1 ((uint32_t)0x00000002) /*!< If 1, indicates that SRC1 was the source of the Soft Reset */
    This macro is intended to check whether the bit for source one is set, e.g.:
    if (RSTCTL->SOFTRESET_STAT & RSTCTL_SOFTRESET_STAT_SRC1) { /* code when watchdog caused a reset here*/ }
    Therefore, you should be able to fix your code by changing line 2 to:
    rst = RSTCTL->SOFTRESET_STAT;
    Also, don't compare a register where each bit has an individual meaning directly with a value. So if you want to check whether bit 1 is set, don't do: if (rst == 2) since that comparison will fail, if bit 1 and 2 are set (then rst will be 6 != 2). Instead use if (rst & 2) , which will work even if other bits are set.
  • 0 in reply to Dan Cermak
    Prodigy 90 points
    Thanks Dan,

    I got the solution.Your solution worked.

    Govind G.

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