CCS/MSP430F5438A: ADC12 configuration with Timer A

Miguel Valera

Tool/software: Code Composer Studio

Hello,

I am very confused with the manner to setup ADC12 sampling time triggered by Timer A. I do not understand how the ADC12SHT0x register works and how this is related with the timer time.

The objective of my code is acquire 5 different signals from 5 ADC channels. The sampling time is 1 ms.

I have different questions on my mind:

1.- Calculating the ADCCLK cycles for 1 kHz, the frequency of ADC12 should be configured at 32768 Hz? with other values I can not obtain a valid value. With this frequency I have 33 CLK cycles.

2.- On this way, do I have to configure the ADC12SHT0x to ADC12SHT0_4(64 cycles)?

3.- Should the timer be configured to count 1 ms too?

4.- On other posts of this forum, I read different ways to program the TA1CCTL0, some people uses the OUTMOD_4 and others OUTMOD_3, Which is the best way to configure it?

I tried to program the configuration of these peripherals in order to the ADC has a 1 ms of sampling time.

Is the code below the suitable way?

//Timer A initialization
void Timer_init (void)
{
	  TA1CCR0 = 33-1;							// Set to 1ms
	  TA1CCR0=0;
	  TA1CTL = TASSEL_1 + MC_1 + TACLR;         // ACLK, upmode, clear TAR
	  TA1CCTL0=OUTMOD_4;
}



// ADC12 Initialization
void ADC12_init (void)
{
	// ADC12 On, S&H 64 cycles, Multiple conversion
	ADC12CTL0=ADC12ON+ADC12SHT0_4+ADC12MSC;

	//Timer A1, SAMPCOM from sampling timer,
	//ADC12CLK=ACLK=32768 Hz and Repeat sequence of channels
	ADC12CTL1=ADC12SHS_1+ADC12SHP+ADC12SSEL_1+ADC12CONSEQ_3;


	ADC12CTL2=ADC12RES_2; //12 bits of resolution (13 cycles)

	ADC12MCTL0 = ADC12INCH_7;                  // Channel = A7
	ADC12MCTL1 = ADC12INCH_12;                 // Channel = A12
	ADC12MCTL2 = ADC12INCH_13;                 // Channel = A13
	ADC12MCTL2 = ADC12INCH_14;                 // Channel = A14
	ADC12MCTL3 = ADC12INCH_15+ADC12EOS;        // Channel = A15, end seq.

	ADC12CTL0|=ADC12ENC;	//Enable conversion
}

Thanks in advance.

Best regards,

Miguel

over 9 years ago

0 James Evans over 9 years ago

TI__Mastermind 49692 points

Hi Miguel,

Let's start with the options for triggering the ADC conversion. This conversion is initiated with a raising edge of the SHI (Sample and Hold Input) signal. As you can see in Figure 28-1 in the User's Guide, there are three timer sources as well as ADC12SC that can be used for SHI. The timer's OUTMOD setting really depends on the timer's mode and if the ADC12ISSH bit is enabled (reverses the polarity of the signal source for SHI).

Let's assume you want to use Timer_A to trigger SHI. In Extended Sample Mode (see Section 28.2.5.1 in the User's Guide), the SHI signal sourced by Timer_A also controls SAMPCON, which directly controls the length of the sample period. In Pulse Sample Mode (see Section 28.2.5.2 in the User's Guide), the SHI signal sourced by Timer_A will trigger SHI, which turns on SAMPCON. However, the big difference here is that SAMPCON in this mode is defined by the ADC12SHTx bits, which specifies the sampling time in 4x multiples of ADC12CLK. ADC12SHT0x selects the sampling time for ADC12MCTL0 to ADC12MCTL7. ADC12SHT1x selects the sampling time for ADC12MCTL8 to ADC12MCTL15.

I'd recommend looking at Figures 28-4 and 28-5 in the User's Guide to easily compare these modes.

Regards,

James

MSP Customer Applications

0 Miguel Valera over 9 years ago in reply to James Evans

Intellectual 340 points

Hi James,

Sorry for the slow answer.

This information is more useful for me. But If I wanna use the Pulse Sample Mode mode, How can I obtain the needed cycles to configure the SHT0x register?

Regards,

Miguel

0 James Evans over 9 years ago in reply to Miguel Valera

TI__Mastermind 49692 points

No problem. First, you'll want to take your sampling time into consideration. Reference Section 28.2.5.3 in the User's Guide to calculate the required sampling time. Then, using this value, you'll want to set the SHT0x register based on the ADC12CLK frequency (which is determined by its source and how it's divided). As I mentioned earlier, each bit in the SHT0x register equals 4x multiples of this ADC12CLK frequency.

As an example, assume you need a sampling time greater than 1 ms. Assuming the ADC12CLK frequency is 100 kHz, its period would be 1 / 100000 Hz which equals 10 us. Thus, you'd want to set SHT0x to something like 0x6 (0110b)which would be a delay of 128 ADC12CLK cycles or 128 * 10 us which equals 1.28 ms (which is greater than a sampling time of 1 ms).

Does this make sense?

Regards,

James

MSP Customer Applications

0 Miguel Valera over 9 years ago in reply to James Evans

Intellectual 340 points

Hi James,

Thank you very much, all my doubts are results in order to ADC.

Should it exist some ralation between frequency of Timer, UART and ADC?

Regards,

Miguel

0 James Evans over 9 years ago in reply to Miguel Valera

TI__Mastermind 49692 points

UART shouldn't affect your Timer_A and ADC configuration, unless your baud rate is so fast that you aren't able to sample fast enough between commands, etc. Obviously, the clock module sourcing the ADC12CLK will need to be much faster than the timer you use to trigger the SHI bit.

Regards,

James

MSP Customer Applications

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CCS/MSP430F5438A: ADC12 configuration with Timer A