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CCS/MSP430F5528: USCI_Bx Interrupt Enable and Flag Registers don't act as expected. UCB1IE=0x03; UCB1IFG=0 don't take effect

Part Number: MSP430F5528


Tool/software: Code Composer Studio

Hello,

I would like to setup the SPI-MASTER Mode for the USCIB1 Module - interrupt handled. 

Setting up by polling the UCBUSY Bit in UCB1STAT Register works - no problem.

But when I try to setup the interrupt, nothing happens.

In CCS I recognized, that the enabling of the two interrupt enable bits in UCB1IE doesn't take any effect. Also the UCB1IFG Register can't be cleared.

My initialisation routine is:

void main(){

...

     UCB1CTL1|=0x01 ; // UCSWRST Reset Hold
     UCB1CTL0|=0x08|0x80; // Master Mode + Positive Edge Sample
     UCB1CTL1|=0x40; // ACLK Select.
     UCB1BR0=1; // LSB Clock Prescaler
     UCB1BR1=0; // MSB Clock Prescaler
                   // UCB1STAT NOTHING TO DO
     UCB1RXBUF=0;  // RX-Buffer zero
                   // UCB1TXBUF nothing to be done
      UCB1IE=0x03; // UCB1IE - Interrupts enabled  - No Effect!
       UCB1IFG=0;               // UCB1IFG cleared - No Effect!!
                      //  UCB1IV nothing to be done
     P4SEL|=0x0e; // MOSI MISO SCK;
     UCB1CTL1&=0xfe; // Clear UCSWRST Reset Hold Bit - SPI READY for USE
__bis_SR_register(GIE);

...

}

and my interrupt service routine (never reached) is given by:

     

#pragma vector=USCI_B1_VECTOR  // Merke: Bezeichner ist im Linker Command File zu finden.
__interrupt void SPIHandler(void){
   char tmp;
   switch(__even_in_range(UCB1IV,0x04)){

   }
    P3OUT ^= 0x04;
}

Could You explain me why I can't set the UCB1IE Bits?? Or what is my mistake??

I'll study the driverlib now - but I prefer understanding the Registers.... thank You!

  • Hello Mathias,

    You need to select synchronous mode (UCSYNC = 1) to use SPI. The RX buffer receives characters from the slave and should never be set by the master, and the TXIFG will remain set so long as the TX buffer is ready for new data and has not been written to. Do you ever set the GIE bit as necessary for entering ISRs? I suggest that you reveiw the MSP430F55xx_uscia0_spi_09.c example.

    Regards,
    Ryan
  • Hello thank You for Your reply,

    I figured out a way how it works: The IE-Bits are to be set AFTER Enabling the Module by clearing the UCSWRST Bit - as documented in the 1.3.1 Section of the USCI-documentation.

    With this in account - everything works fine.

    I'll check Your feedback regarding USync also - but don't face any problems or missbehaviour till now.

    Thank You
    With best Regards
    Mathias

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