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MSP430F5419A: system going to stuck

Part Number: MSP430F5419A


Hello Everyone,

 1.  I am working on three phase energy meter application with msp430 as Master and Ade7880 as slave using SPI communication.

  2 . working on MCLK= 16 MHZ  DCO clock  and for peripheral we are used XTL2 = SMCLK =4 MHZ.

following thing are facing 

scenario 1:  Without AC supply and load.  (current and voltage are zeros).Only supply Provides to MCU (3.3 V).

                      Whenever switching is doing ON to OFF  Or OFF to ON , problem is not coming ,BUT

scenario 2:  With AC supply and load. 

Whenever switching is doing ON to OFF  Or OFF to ON , microcontroller gets stuck on unexpected random locations

and sometimes stopping the cpu execution on do-while loop , library functions like printf, strstr functions.   

It is stcuking at  very small loads (15 Watt) .

 

Facing problem on scenario 2. 

Is that clock issue or core voltage issue Or any other issue.

please check following code clock init and setting of core voltage.

 

//Clock Intialization ==> MCLK=16MHZ SMCLK=4MHZ ACLK=32KHZ
void clock_init()
{

SetVcoreUp(PMMCOREV_1);
SetVcoreUp(PMMCOREV_2); // Set VCore to 1.8v for 20MHz


P11DIR = BIT2 + BIT1 + BIT0; // P11.2,1,0 to output direction

P11SEL = BIT2 + BIT1 + BIT0; // P11.2 to output SMCLK, P11.1

// to output MCLK and P11.0 to
// output ACLK
P5SEL |= 0x0C; // Port select XT2
P7SEL |= 0x03; // Port select XT1

UCSCTL6 &= ~(XT1OFF + XT2OFF); // Set XT1 & XT2 On
UCSCTL6 |= XCAP_3; // Internal load cap

// Loop until XT1,XT2 & DCO stabilizes
     do
       {
          UCSCTL7 &= ~(XT2OFFG + XT1LFOFFG + XT1HFOFFG + DCOFFG);

// Clear XT2,XT1,DCO fault flags
SFRIFG1 &= ~OFIFG; // Clear fault flags

}while (SFRIFG1&OFIFG); // Test oscillator fault flag

UCSCTL6 &= ~XT2DRIVE0; // Decrease XT2 Drive according to

UCSCTL3 |= SELREF_2; //SELREF__XT2CLK;//SELREF__XT2CLK ; //SELREF_5;

__bis_SR_register(SCG0); // Disable the FLL control loop

UCSCTL0 |=0x0000;

UCSCTL1|=DCORSEL_7;

UCSCTL2 |= FLLD_1 + 488;


__bic_SR_register(SCG0); // Disable the FLL control loop

__delay_cycles(500000);  //settle DCO

UCSCTL4 |= SELA_2 + SELS_5 ;//+ SELM_3;

}

//Configured PMM control registers SVM,SVS Control registers
void SetVcoreUp (unsigned int level)
{
// Open PMM registers for write
PMMCTL0_H = PMMPW_H; //PMM password always 0x45 for writing and 0x96 for reading
// Set SVS/SVM high side new level
SVSMHCTL = SVSHE + SVSHRVL0 * level + SVMHE + SVSMHRRL0 * level;
// Set SVM low side to new level
SVSMLCTL = SVSLE + SVMLE + SVSMLRRL0 * level;
// Wait till SVM is settled
while ((PMMIFG & SVSMLDLYIFG) == 0);
// Clear already set flags
PMMIFG &= ~(SVMLVLRIFG + SVMLIFG);
// Set VCore to new level
PMMCTL0_L = PMMCOREV0 * level;
// Wait till new level reached
if ((PMMIFG & SVMLIFG))
while ((PMMIFG & SVMLVLRIFG) == 0);
// Set SVS/SVM low side to new level
SVSMLCTL = SVSLE + SVSLRVL0 * level + SVMLE + SVSMLRRL0 * level;
// Lock PMM registers for write access
PMMCTL0_H = 0x00;
}

Please help me to solve this stuck problem.

 

Regards,

Sanjay M.

 



  • Hello Sanjay,

    UCSCTL6 should be clearing XT2DRIVE_3 for the operating range of 4 to 8 MHz. As shown in the TI-provided UCS examples, UCSCTL[0,1,2] are typically simply assigned (=) instead of being bit assigned (|=). The clock stabilization loop should also occur after all clocks have been initialized and allowed time to settle, located before setting up the dividers in UCSCTL4. But these changes will only make a slight difference to the clock operation and should not be the cause of the issue described. You could increase the core to level 3 to see if this improves the system behavior.

    Please make sure that the Vcore capacitance is 470 nF and that there are > 4.7 uF decoupling capacitors on the VCC pins. Can you provide an oscilloscope screenshot of Vcc, MCLK, SMCLK, ACLK, and RST when the issue occurs? Do XT1 and XT2 continue to oscillate? Is the MCU in a LPM when the switching occurs and does the problem happen every time?

    Regards,
    Ryan

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