Other Parts Discussed in Thread: MSP430G2744, MSP430F5528
Dear TI Team,
Currently I´m writing a custom Bootloader for the MSP430G2744 Mcu. When I´m finished with these task, I will start with porting the Bootloader to a MSP430F5528 Mcu.
I have several questions about Linking process on these devices. CCS Versions is 5.5, current Compiler Version is TI v4.2.1
Firstly, I will need a copy of the Vector Table at runtime. Is it possible to make this step automated while flashing the device with SBW? I want that the Linker generates a second Table at a specific Location. My first attempt was simply to create a second Section for the Copy and write the table to both locations. But the second location is not written and stays with initial FLASH Value of 0xFF
part of my Linker command file:
vect_table : {} > VECTOR_TABLE
vect_table : {} > VECTOR_TABLE_COPY
My Second question is about the Vector Table in the F5xx Devices and the MSP430X Architecture. Where are the Interrupt handlers linked when Large Memory Model for Code is specified? e.g. 20 Bit width pointers
Is it guaranteed that the Interrupt Handlers are always linked to the lower 65K Region due to Hardware limitations? If not, how the Hardware handles the case, if some Handlers are placed in the higher Memory, while others are in the lower Region?
Relocating .text:_isr to FLASH2 in the linker Command File seems not to throw any errors at the Linking process,
but to be honest, i did not run the programm with this modification:
.text:_isr : {} > FLASH2 /* ISR CODE SPACE */
