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Starterware/MSP430FR6972: The question of DMA

Jent
Intellectual 660 points
Part Number: MSP430FR6972

Tool/software: Starterware

Hello , 

I  want to use DMA tran tansmit ADC data to FRAM . The ADC mode is Repeat-Sequence-of-Channels Mode  from ADC12MCTL0 to ADC12MCTL1, ADC trigger signal is  TA0.1 . the code is following

//ADC12(internal) trigger ,TA0.1 PWM 8.192KHz from 32.768KHz crystal oscillator
TA01_PWMOUT(4, 2, TASSEL__ACLK);
// Set ADC channel pins
ADC_Pin_Set();

ADC12CTL0 &= ~ADC12ENC;
ADC12CTL0 |= ADC12ON;

//ADC12_B sample-and-hold time 
ADC12CTL0 |= ADC12SHT1_1;
//a rising edge of the SHI signal to trigger each sample-and-convert
ADC12CTL0 &= ~ADC12MSC;
// ADC trigger TA0.1, ADC clock is SMCLK
ADC12CTL1 |= ADC12SHP |  ADC12SHS_1 | ADC12PDIV__1 | ADC12DIV_0 | ADC12SSEL_3;
// Repeat-sequence-of-channels
ADC12CTL1 |= ADC12CONSEQ_3;
//12bit ADC
ADC12CTL2 |= ADC12RES_2;
//Start Mem
ADC12CTL3 = ADC12CSTARTADD_0;
//MemCtl set
ADC12MCTL0 |= ADC12INCH_2 | ADC12VRSEL_1;
ADC12MCTL1 |= ADC12INCH_3 | ADC12VRSEL_1;
//End Mem
ADC12MCTL1 |= ADC12EOS;

//DMA Set
DMACTL0 |= DMA1TSEL__ADC12IFG;    
__data16_write_addr((unsigned short) &DMA1SA,(INT16U)  &ADC12MEM1);                                               
__data16_write_addr((unsigned short) &DMA1DA,(INT16U)  &ElecfieldBuffer[0]); 	
DMA1SZ = 5120;   
DMA1CTL = DMADT_4 | DMADSTINCR_3 | DMASRCINCR_0 |DMASWDW |DMAEN ;

"When CONSEQx = {1,3}, theADC12IFG flag for the last ADC12MEMx in the sequence can trigger a DMA transfer. " (Page 336 of MSP430FR6972 User's Guide) . I know  that  only the ADC12IFG of ADC12MEM1 can trigger a DMA transfer , But I found it not as . The DMA wasted 625ms to accomplish 5120 points . However,the theory of time shoud be (1/8.192KHz) * 2 * 5120  = 1250ms . Why is it ?

Best Regards,

Jent

  • 0
    Intellectual 660 points

    May be any ADC12FIG  trigger DMA tansfer. I found the earch two values in the array is same ..

     

  • 0 in reply to Jent
    TI__Guru**** 212557 points
    With 5120 word transfers every 122 microseconds (same sample frequency as the timer for sequence-of-conversions) I would expect the total time to be 625 ms, can you explain why you expect a different result? When sequences-of-conversions are used, the ADC12IFG for the last conversion in the sequence is the trigger for the DMA. The duplicate array values could be coincidental since the value is not changing drastically, could you provide more data to prove your theory? Please confirm your timer frequency as well.

    Regards,
    Ryan
  • 0 in reply to Ryan Brown1
    Intellectual 660 points

    thank you Ryan ,

       I set the sequence  mode and every convesion must be trigger by TA0.1, so A2 will be converted  at the frist 122miscroseconds , A3 will be converted  at the second 122 miscroseconds ,then A2 will be converted at the third   122 miscrosecondes again.  In conclusion ,  the sample time of A2 is 244 miscroseconds , A3 is the same as A2.    It will cost  5120 X  244 = 1250ms  to  transmit 5120 word .

       I  found the reason from MSP430FR6972 Device Erratasheet(Page 3), But I thought the workaround doesn't fit my demand. I want  the A2 and A3 will be stored in two array[5120] continuously without using interrupt . Do you have good idea ?

    Best Ragards

    Jent

  • 0 in reply to Jent
    TI__Guru**** 212557 points
    Thank you for further explaining your application Jent, I understand what you are trying to accomplish now and the ADC43 errata does appear to detail the issue you are experiencing. The easiest solution is to use single channel conversions to sample one input 5120 times then switch to the next input and repeat, but this won't work if you need to sample the two input simultaneously. Since you must trigger on each conversion my suggestion is to use two DMA channels, both of which use the same trigger but whose source and destination are different (ADCMEM1 to ElecfieldBuffer and ADCMEM0 to CurrentFaultBuffer). Since there will be duplicates (2 of each sample transferred) you must either double your array sizes (10240) or stop halfway through (2560), clear out the extra data, and then continue to sample the second half. But this will still require an extra array size (7680) with dead space (2560) at the end of the array once all of the data has been organized accordingly. The least favorable alternative is interrupting repeatedly to arrange the information as required. I see a few options but cannot determine a complete workaround to your dilemma.

    Regards,
    Ryan
  • 0 in reply to Jent
    TI__Guru**** 212557 points
    If you could handle storing both ADC12MEM0 and ADC12MEM1 values in a single large array then a possible solution is to use a second DMA channel with the same trigger but lower priority (and in repeated single transfer mode) to change the source address of the first channel between ADC12MEM0 and ADC12MEM1, this would result in an uninterrupted transfer of 10240 bytes (1st sample A2, 1st sample A3, 2nd sample A2, 2nd sample A3, etc.)

    Regards,
    Ryan

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