MSP430AFE252: Change TA1 PWM output based on SD24 input

//******************************************************************************
//  MSP430AFE25x Demo - Timer_A, PWM TA1, Up/Down Mode, DCO SMCLK
//
//  Description: This program generates one PWM output on P1.1 using
//  Timer_A configured for up/down mode. The value in CCR0, 128, defines the PWM
//  period/2 and the value in CCR1 the PWM duty cycles.
//  A 75% duty cycle is on P1.1.
//  SMCLK = MCLK = TACLK = default DCO
//
//               MSP430AFE25x
//            -----------------
//        /|\|              XIN|-
//         | |                 |
//         --|RST          XOUT|-
//           |                 |
//           |         P1.1/TA1|--> CCR1 - 75% PWM
//
//  Naveen Kala
//  Texas Instruments, Inc
//  March 2011
//  Built with IAR Embedded Workbench Version: 5.20.1
//******************************************************************************
#include <msp430afe253.h>

#define   Num_of_Results   8

/* Arrays to store SD24 conversion results */
unsigned int Ch0results[Num_of_Results];
unsigned int Ch1results[Num_of_Results];
unsigned int Ch2results[Num_of_Results];

void main(void)
{
	
	
volatile unsigned int i;                  // Use volatile to prevent removal
                                            // by compiler optimization

  WDTCTL = WDTPW + WDTHOLD;                 // Stop WDT

  P1DIR |= BIT0+BIT1;                       // Set P1.0, P1.1 to output
  SD24CTL = SD24REFON + SD24SSEL0;          // 1.2V ref, SMCLK
  SD24CCTL0 |= SD24GRP+SD24DF;              // Group with CH1
  SD24CCTL1 |= SD24GRP+SD24DF;              // Group with CH2
//  SD24CCTL2 |= SD24IE+SD24DF;               // Enable interrupt
  for (i = 0; i < 0x3600; i++);             // Delay for 1.2V ref startup
  
  SD24CCTL1 |= SD24SC;                      // Set bit to start conversion

    P1DIR |= BIT0;                            // Set P1.0 to output direction
 // SVSCTL = 0x60 + PORON;                    // SVS POR enabled @ 2.5V
  	
  WDTCTL = WDTPW + WDTHOLD;                 // Stop WDT
  P1DIR |= BIT3 + BIT1;                     // P1.1 and P1.3 output
  P1SEL |= BIT3 + BIT1;                     // P1.1 and P1.3 TA1/2 options
  CCR0 = 128;                               // PWM Period/2
  CCTL1 = OUTMOD_6;                         // CCR1 toggle/set
  CCR1 = 64;                                // CCR1 PWM duty cycle
  TACTL = TASSEL_2 + MC_3;                  // SMCLK, up-down mode
  
 // __bis_SR_register(LPM0_bits + GIE);       // Enter LPM0 w/ interrupts
 // _BIS_SR(LPM0_bits);                       // Enter LPM0
 while(1)
 {
   	CCR1 = Ch0results[1]/500;//65535
   	P1OUT ^= BIT0;
 }
}

#pragma vector=SD24_VECTOR
__interrupt void SD24AISR(void)
{
      static unsigned int index = 0;
    
      switch (SD24IV)
      {
      case 2:                                   // SD24MEM Overflow
        break;
      case 4:                                   // SD24MEM0 IFG
        break;
      case 6:                                   // SD24MEM1 IFG
        break;
      case 8:                                   // SD24MEM2 IFG
        Ch0results[index] = SD24MEM0;           // Save CH0 results (clears IFG)
        Ch1results[index] = SD24MEM1;           // Save CH1 results (clears IFG)
      //  Ch2results[index] = SD24MEM2;           // Save CH2 results (clears IFG)

        break;
      }
}