Errate USCI43 in MSP432P401R Device Erratasheet.
What's the synchronous clock sources?
I use the SMCLK for the I2C block, and SMCLK is sourced from MCLK with 2 diviver. Is it the workaround 1?
Does anynone know it?
Thanks!
Function: I2C communication stalled when polling UCBxRXIFG
Description: When using the USCI_B I2C module as a receiver, if an asynchronous event occurs during the read of the UCBxRXIFG interrupt flag, the flag could be unintentionally cleared. This may result in the I2C communication being stalled.
Workaround: 1. If the device functions as an I2C master receiver, use synchronous clock sources for operation.
OR
2. Avoid polling UCBxRXIFG. Using the standard interrupt service routine to service the UCBxRXIFG interrupt flag significantly reduces the probability of this errata occurring. Avoid register access to UCBxCTLW0, UCBxSTATW, UCBxRXBUF, UCBxTXBUF, UCBxIFG, & UCBxIV while transmit or receive operation is ongoing and UCBxRXIFG or UCBxTXIFG is expected to be set.
OR
3. Use the clock low time-out select feature (UCCTLO.UCBxCTLW1) to enable a timeout window. In the event that the I2C communication is stalled, use the clock low time-out interrupt to reset the eUSCI module and re-initiate communication.
