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MSP432P401R: Example Project for MSP432 Clock Initilization

Part Number: MSP432P401R

Hi Team,

For all example project, we use the default clock configuration. 

Do we have a plan for Clock Configuration Example? Thanks.

  • Hello LLouis,

    Just to be on the same page, which examples are referring to??

    Thanks,

    David
  • Hi David,

    I would need a clock configuration demo project with TI-RTOS. Thanks.
  • Hello LLouis,

    When you say "a clock configuration demo project", that means that you need an example to change MCLK, HSMCLK and SMCLK?? If that is the case you will need to enable the "custom performance levels".  By default the Power Diver supports  four pre-defined performance levels, please read below:

    /* The MCU performance level can be set with Power_setPerformanceLevel().
     *  A performance level is defined by this PowerMSP432_PerfLevel structure.
     *
     *  The Power driver currently supports four pre-defined performance levels:
    *
     *    Level    MCLK (MHz)    HSMCLK (MHz)    SMCLK (MHz)    ACLK (Hz)
     *    -----    ----------    ------------    -----------    ---------
     *      0         12              3              3           32768
     *      1         24              6              6           32768
     *      2         48             24             12           32768
     *      3         48             48             24           32768
     *
     *  Up to four optional 'custom' performance levels can be defined by the user.
     *  Performance levels are designated by an index, starting with
     *  zero.  Any custom performance levels will be indexed following the last
     *  pre-defined level.  For example, if there are 4 pre-defined levels, they
     *  will have indices from '0' to '3'. If there are custom levels defined, they
     *  will be indexed starting with '4'.
     *
     *  To define custom performance levels the user must add an array of
     *  PowerMSP432_PerfLevel structures to their board file, and then reference
     *  this array in the PowerMSP432_config structure. An example is shown
     *  below.
     *
     *  First, if not already included in the board file, add the includes of cs.h
     *  and pcm.h
     *
     *  #include <ti/devices/msp432p4xx/driverlib/cs.h>
     *  #include <ti/devices/msp432p4xx/driverlib/pcm.h>
     *
     *  Next, add an array with two new performance levels:
     *
     *  PowerMSP432_PerfLevel myPerfLevels[] = {
     *    {
     *      .activeState = PCM_AM_DCDC_VCORE0,
     *      .VCORE = 0,
     *      .clockSource = CS_DCOCLK_SELECT,
     *      .DCORESEL = CS_DCO_FREQUENCY_12,
     *      .DIVM = CS_CLOCK_DIVIDER_1,
     *      .DIVHS = CS_CLOCK_DIVIDER_4,
     *      .DIVS = CS_CLOCK_DIVIDER_4,
     *      .flashWaitStates = 0,
     *      .enableFlashBuffer = false,
     *      .MCLK = 12000000,
     *      .HSMCLK = 3000000,
     *      .SMCLK = 3000000,
     *      .ACLK = 32768
     *    }
     *  };
     *  And then reference the new custom levels by adding the following to the
     *  end of the PowerMSP432_config structure:
     *
     *  const PowerMSP432_ConfigV1 PowerMSP432_config = {
     *      ...
     *      .customPerfLevels = myPerfLevels,
     *      .numCustom = sizeof(myPerfLevels) / sizeof(PowerMSP432_PerfLevel)
     *  };
     */

    Is this what you need?? FYI - this feature was implemented on the SimpleLink MSP432 SDK v1.30.00.40

      Best regards,

        David

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