MSP430F5529: i2c slave tx to master example code fails - MSP430F55xx_Uscib0_i2c_10.c

//******************************************************************************
//
// Slave code
// - slave transmits to master
//
// This is copied from MSP430F55xx_uscib0_i2c_11.c
//******************************************************************************
#include <msp430.h>

unsigned char *PTxData; // Pointer to TX data
const unsigned char TxData[] = // Table of data to transmit
{
0x11,
0x22,
0x33,
0x44,
0x55
};

int main(void)
{
WDTCTL = WDTPW + WDTHOLD; // Stop WDT
P3SEL |= 0x03; // Assign I2C pins to USCI_B0
UCB0CTL1 |= UCSWRST; // Enable SW reset
UCB0CTL0 = UCMODE_3 + UCSYNC; // I2C Slave, synchronous mode
UCB0I2COA = 0x48; // Own Address is 048h
UCB0CTL1 &= ~UCSWRST; // Clear SW reset, resume operation
UCB0IE |= UCTXIE + UCSTPIE + UCSTTIE; // Enable STT and STP interrupt
// Enable TX interrupt

while (1)
{
PTxData = (unsigned char *)TxData; // Start of TX buffer

__bis_SR_register(LPM0_bits + GIE); // Enter LPM0, enable interrupts
// Remain in LPM0 until master
// finishes RX
__no_operation(); // Set breakpoint >>here<< and
} // read out the TXByteCtr counter
}

//------------------------------------------------------------------------------
// The USCI_B0 data ISR TX vector is used to move data from MSP430 memory to the
// I2C master. PTxData points to the next byte to be transmitted, and TXByteCtr
// keeps track of the number of bytes transmitted.
//------------------------------------------------------------------------------
//------------------------------------------------------------------------------
// The USCI_B0 state ISR TX vector is used to wake up the CPU from LPM0 in order
// to do processing in the main program after data has been transmitted. LPM0 is
// only exit in case of a (re-)start or stop condition when actual data
// was transmitted.
//------------------------------------------------------------------------------
#if defined(__TI_COMPILER_VERSION__) || defined(__IAR_SYSTEMS_ICC__)
#pragma vector = USCI_B0_VECTOR
__interrupt void USCI_B0_ISR(void)
#elif defined(__GNUC__)
void __attribute__ ((interrupt(USCI_B0_VECTOR))) USCI_B0_ISR (void)
#else
#error Compiler not supported!
#endif
{
switch(__even_in_range(UCB0IV,12))
{
case 0: break; // Vector 0: No interrupts
case 2: break; // Vector 2: ALIFG
case 4: break; // Vector 4: NACKIFG
case 6: // Vector 6: STTIFG
UCB0IFG &= ~UCSTTIFG; // Clear start condition int flag
break;
case 8: // Vector 8: STPIFG
UCB0IFG &= ~UCSTPIFG; // Clear stop condition int flag
__bic_SR_register_on_exit(LPM0_bits); // Exit LPM0 if data was transmitted
break;
case 10: break; // Vector 10: RXIFG
case 12: // Vector 12: TXIFG
UCB0TXBUF = *PTxData++; // Transmit data at address PTxData
break;
default: break;
}
}

//******************************************************************************
//
// Master code
// - Master receives data from slave 
//
//
// This is copied from MSP430F55xx_uscib0_i2c_10.c
//
//******************************************************************************

#include <msp430.h>

unsigned char *PRxData; // Pointer to RX data
unsigned char RXByteCtr;
volatile unsigned char RxBuffer[128]; // Allocate 128 byte of RAM

int main(void)
{
WDTCTL = WDTPW + WDTHOLD; // Stop WDT
P3SEL |= 0x03; // Assign I2C pins to USCI_B0
UCB0CTL1 |= UCSWRST; // Enable SW reset
UCB0CTL0 = UCMST + UCMODE_3 + UCSYNC; // I2C Master, synchronous mode
UCB0CTL1 = UCSSEL_2 + UCSWRST; // Use SMCLK, keep SW reset
UCB0BR0 = 12; // fSCL = SMCLK/12 = ~100kHz
UCB0BR1 = 0;
UCB0I2CSA = 0x48; // Slave Address is 048h
UCB0CTL1 &= ~UCSWRST; // Clear SW reset, resume operation
UCB0IE |= UCRXIE; // Enable RX interrupt

while (1)
{
PRxData = (unsigned char *)RxBuffer; // Start of RX buffer
RXByteCtr = 5; // Load RX byte counter
while (UCB0CTL1 & UCTXSTP); // Ensure stop condition got sent
UCB0CTL1 |= UCTXSTT; // I2C start condition

__bis_SR_register(LPM0_bits + GIE); // Enter LPM0, enable interrupts
// Remain in LPM0 until all data
// is RX'd
__no_operation(); // Set breakpoint >>here<< and
} // read out the RxBuffer buffer
}

//-------------------------------------------------------------------------------
// The USCI_B0 data ISR is used to move received data from the I2C slave
// to the MSP430 memory. It is structured such that it can be used to receive
// any 2+ number of bytes by pre-loading RXByteCtr with the byte count.
//-------------------------------------------------------------------------------
#if defined(__TI_COMPILER_VERSION__) || defined(__IAR_SYSTEMS_ICC__)
#pragma vector = USCI_B0_VECTOR
__interrupt void USCI_B0_ISR(void)
#elif defined(__GNUC__)
void __attribute__ ((interrupt(USCI_B0_VECTOR))) USCI_B0_ISR (void)
#else
#error Compiler not supported!
#endif
{
switch(__even_in_range(UCB0IV,12))
{
case 0: break; // Vector 0: No interrupts
case 2: break; // Vector 2: ALIFG
case 4: break; // Vector 4: NACKIFG
case 6: break; // Vector 6: STTIFG
case 8: break; // Vector 8: STPIFG
case 10: // Vector 10: RXIFG
RXByteCtr--; // Decrement RX byte counter
if (RXByteCtr)
{
*PRxData++ = UCB0RXBUF; // Move RX data to address PRxData
if (RXByteCtr == 1) // Only one byte left?
UCB0CTL1 |= UCTXSTP; // Generate I2C stop condition
}
else
{
*PRxData = UCB0RXBUF; // Move final RX data to PRxData
__bic_SR_register_on_exit(LPM0_bits); // Exit active CPU
}
break;
case 12: break; // Vector 12: TXIFG
default: break;
}
}