I have implemented SPI 4-wire Slave with MSP430F5359. My expectation was that Chip Select (CS) would reset bits count every time the CS is de-asserted, which would maintain byte synchronization. However, I noticed that actually, the CS works more like a gate. It does not reset the SPI state machine at all. So, for example, if due to a noise in the clock signal, an extra clock happened, then an extra bit would be registered and the entire bits sequence becomes shifted by one bit and stays shifted forever. The question is, is that the intended behavior that CS does not reset the bits count in SPI slave of this microprocessor or I am missing something in SPI settings?