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MSP430F5359: SPI Slave Chip Select behavior

Part Number: MSP430F5359

I have implemented SPI 4-wire Slave with MSP430F5359. My expectation was that Chip Select (CS) would reset bits count every time the CS is de-asserted, which would maintain byte synchronization.  However, I noticed that actually, the CS works more like a gate. It does not reset the SPI state machine at all. So, for example, if due to a noise in the clock signal, an extra clock happened, then an extra bit would be registered and the entire bits sequence becomes shifted by one bit and stays shifted forever. The question is, is that the intended behavior that CS does not reset the bits count in SPI slave of this microprocessor or I am missing something in SPI settings?

  • Hello Ruslan,

    The SPI 4-wire USCI configuration found within the MSP430F5359, does not implement a CS. The fourth wire is the STE (Slave Transmit Enable) signal that is used in systems with multiple masters. It main purpose is to prevent conflict between multiple masters on a bus. It is not a CS signal. Some MSP430s do allow the STE signal to be used as a CS with additional register settings, but it still behaves differently from a traditional CS. Please see Section 4.3 Various Implementations of Chip Select (CS) in the following application note for more information about the STE signal and how to implement CS.

    www.ti.com/lit/slaa734

  • Thank you Jace. I wish it was a "traditional" SPI Slave CS implementation so I did not need any extra coding for byte re-synchronization. Anyways, you have answered my question. Now I know what the problem is and how to resolve it. Thanks for the quick and detailed response. I really appreciate your support.
  • Ruslan,

    I would advise using the same pin, but configuring it as a GPIO interrupt. Within said interrupt you can reset the SPI state machine or hold the USCI in reset until the next interrupt. For example, if you wish for the CS to be active high, the configure GPIO for interrupt on low to high transition. Within interrupt turn on USCI in SPI mode, then set GPIO interrupt trigger to a High to Low transition. When CS pin goes low, then the interrupt will fire again. This time you can hold the USCI in Reset and reconfigure interrupt for low to high transition.
  • Thank you for the recommendation. I will try to use GPIO interrupt to control SPI state machine.

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