Part Number: MSP430FR5969
On page 661 of "SLAU367M–October 2012–Revised January 2017", bit 12 of UCBxIFG (UCRXIFG3) is incorrectly described as :
"Receive interrupt flag 2. UCRXIFG2 is set when UCBxRXBUF has received a
complete byte in slave mode and if the slave address defined in UCBxI2COA2
was on the bus in the same frame."
The curse of cut-n-paste!
Minor, but, hey...
