11.2.3 Initiating DMA Transfers Each DMA channel is independently configured for its trigger source with the DMAxTSEL. The DMAxTSEL bits should be modified only when the DMACTLx DMAEN bit is 0. Otherwise, unpredictable DMA triggers may occur. Table 11-2 describes the trigger operation for each type of module. See the device-specific data sheet for the list of triggers available, along with their respective DMAxTSEL values. When selecting the trigger, the trigger must not have already occurred, or the transfer does not take place.
should read as follows:
11.2.3 Initiating DMA Transfers Each DMA channel is independently configured for its trigger source with the DMAxTSEL. The DMAxTSEL bits should be modified only when the DMAxCTL DMAEN bit is 0. Otherwise, unpredictable DMA triggers may occur. Table 11-2 describes the trigger operation for each type of module. See the device-specific data sheet for the list of triggers available, along with their respective DMAxTSEL values. When selecting the trigger, the trigger must not have already occurred, or the transfer does not take place.
Further:
the device specific datasheet - msp430fr5994.pdf - omits the footnote on page 135 stating: "When writing to DMAxSA with word instructions, bits 19-16 are cleared." inserted at each DMAxxAH line.
If bits 19-16 are not cleared, the footnote is still required for clarification.
