MSP430F149: Apply 8MHz as MCLK.

Bin Sun

Intellectual 360 points

Part Number: MSP430F149

Hi, all.

I am using the XT2 8MHz crystal as clock source.

The SMCLK is 8MHZ devided by 4 as 2MHz. The MCLK is 8MHZ devided by 1 as 8MHz.

I measured the SMCLK and MCLK on the P5.5 and P5.4.

I am pretty sure the XT2 is working because the signal from P5.5 is 2MHz.

My problem is that the MCLK is not 8MHz as I design. It is 747kHz.

The DVcc is 3.36V.

Here is the code:

BCSCTL2 |= SELM_2+DIVM_0+SELS+DIVS_2; // MCLK= XT2 8M //SMCLK=XT2/4 2M

Any idea on the problem?

over 9 years ago

0 Ryan Brown1 over 9 years ago

TI__Guru**** 223827 points

Hi Bin,

Please run code example fet140_hfxt2.c to verify that MCLK is not operating as expected. www.ti.com/.../slac015

Regards,
Ryan

0 Clemens Ladisch over 9 years ago

Guru 327330 points

This sounds as if the oscillator fault logic has forced MCLK to run from the DCO. You have not shown your entire code, but I guess you did not do what section 4.2.6 of the User's Guide tells you to do.

0 Bin Sun over 9 years ago in reply to Ryan Brown1

Intellectual 360 points

Hi, I fixed the problem according to the file.

Thanks.

What is the maximum frequency of the IO?

I used 2MHz in the timer A.

Sometimes, the P1.0 needs to go high from low after 4 counts(2us). But it is not going to high.

Any idea?

0 Bin Sun over 9 years ago in reply to Clemens Ladisch

Intellectual 360 points

Yes. You are right. It is solved.

0 Ryan Brown1 over 9 years ago in reply to Bin Sun

TI__Guru**** 223827 points

If you are simply driving the pin through software (P1.0 high and low, as it has no timer output capability) then it will be hard to create the desired frequency. Using the timer can result in a dependable period (500 kHz, TA0/CCR0 set to four) with outputs driven at the PWM pins (TA1/CCR1 & TA2/CCR2, set to two for 50% duty cycle). You should increase the SMCLK frequency sourcing TA0 for greater accuracy in creating a high-frequency timer output. There are code examples from TI that should be referenced.

Regards,
Ryan

0 Bin Sun over 9 years ago in reply to Ryan Brown1

Intellectual 360 points

Hi, actually I am doing SPWM through P1.0. The period is 400 counts, and duty cycle is ranging from 0 to 100%. The problem I mentioned occured when the duty cycle is 99%(the 4 counts is the low period). P1.0 should raise to high after that control cycle. But P1.0 is not toggled after 4 counts. It keeps low. Any idea on it? May be the duty cycle is too high?

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MSP430F149: Apply 8MHz as MCLK.