MSP430L092: Performing ADC conversions at same time as DAC is being used

Hello Robert,

We have received your question. We will get back to you shortly.

Can you please provide your code?

Hello,

Below is the relevant code for the problem...note that I am polling for the EOC flag rather than using interrupts. This is to maximize performance that is needed in the final product.

#include "msp430.h" ; #define controlled include file
#include "msp430.h" ; #define controlled include file

NAME main ; module name

PUBLIC main ; make the main label visible
; outside this module

#define FREQ_VALUE 140
;
; IO port definitions
;
;
; P1
;
E_AMP_OUT2 EQU 0x01
RX_DATA EQU 0x02
CHANNEL_DAC EQU 0x04
VREF EQU 0x08
E_AMP_OUT1 EQU 0x10
TEST1 EQU 0x20
TX_DATA EQU 0x40

;
; Interrupt Vectors
;
ORG 0FFE0h
DC16 INVINT ; invalid interrupt -- just return
DC16 INVINT ; invalid interrupt -- just return
DC16 INVINT ; invalid interrupt -- just return
DC16 INVINT ; invalid interrupt -- just return
DC16 INVINT ; invalid interrupt -- just return
DC16 INVINT ; I?O Port P2 (P2IFG.0 to P2FIG.3)
DC16 INVINT ; Timer0_A3 (TA0CCR1 CCIFG1) - Sample Interrupt
DC16 INVINT ; Timer0_A3 (TA0CCR0 CCIFG0) - Transmit Interrupt
DC16 INVINT ; I/O Port P1 (P1IFG.0 to P1IFG.6)
DC16 INVINT ; A-Pool (CxIFG)
DC16 WDTIRQ ; WDTIFG
DC16 INVINT ; Timer1_A3 (TA1CCR1 CCIFG1)
DC16 INVINT ; Timer1_A3 (TA1CCR0 CCIFG0) - Transmit Interrupt
DC16 USERNMI ; User NMI (NMIFLG)
DC16 SYSTEMNMI ; System NMI (SVMIFG, VMAIFG)
DC16 init ; reset vector address

RSEG CSTACK ; pre-declaration of segment
RSEG CODE ; place program in 'CODE' segment

init: MOV #SFE(CSTACK), SP ; set up stack

main: NOP ; main program
MOV.W #WDTPW+WDTHOLD,&WDTCTL ; Stop watchdog timer
;
; Initialize I/O pins
; set unused i/o pins to output-0
;
BIS.B #TX_DATA,&P1DIR ; set test pin as output

; turn transmitter on at startup for testing <<<
BIC.B #TX_DATA,&P1OUT ; turn transmit on

MOV.W #VREFEN+APREFON+DBON+CONVON,&APCNF ; Enable DAC buffer, conversion, and reference
; and setup ADC inputs
MOV.W #ODEN+OSEL,&APCTL ; set DAC output to pin, select output buffer
MOV.W #FREQ_VALUE,&APINT
BIC.W #DBON,&APCNF

;
; Setup Clocks
;
MOV.W #CCSKEY,&CCSCTL0 ; Unlock CCS
Clock1 MOV.W #0,&CCSCTL7 ; Clear HF and LF OSC startup fault conditions
MOV.W #0,&SFRIFG1 ; Clear OFIFG
BIT.W #OFIFG,&SFRIFG1 ; Oscillator flags?
JNZ Clock1
MOV.W #0000h,&CCSCTL4 ; set ACLK, SMCLK, and MCLK back to HFCLK
MOV.W #DIVA_0+DIVS_0+DIVM_0,&CCSCTL5 ; ACLK/1 (1000 KHz), SMCLK /1 (1000 KHz (default), and MCLK /1 (1000 KHz)
MOV.B #0FFh,&CCSCTL0_H ; Lock CCS

#if 1 ; ADC conversion
MOV.W #CMPON+VREFEN+APREFON+DBON+CLKSEL1+CONVON,&APCNF ; Enable DAC buffer,
BIC.W #REFTSEL,&APTRIM ; turn off reference trim register
; Begin Configuration of the A-POOL registers

MOV.W #0,&APCTL ; Clear APCTL register
MOV.W #REFTSEL,&APTRIM
MOV.W #TMPSEN,&APVDIV ; Enable Temperature Sensor
MOV.W #CMPON+DBON+CLKSEL_MCLK+CONVON+APREFON,&APCNF ; Configure A-POOL elements, Select MCLK as A-POOL Clock Source
MOV.W #OSEL+ODEN+APPSEL_5+APNSEL_4,&APCTL ; Set Channels and Start Conversion
TESTRX0
MOV.W #0,&APINT
BIS.W #RUNSTOP+CBSTP+SBSTP,&APCTL ; start conversion
TESTRX1
BIT.W #EOCIFG,&APIFG ; wait for conversion complete flag
JZ TESTRX1
MOV.W #0,&APIFG
BIC.W #RUNSTOP,&APCTL
MOV.W &APINT,R10 ; get sensor data
NOP
JMP TESTRX0
#endif

;
; go to sleep awaiting interrupts
;
BIS.W #GIE+SCG1+CPUOFF,SR ; go to LPM2 (LPM2 is used instead of
; LPM3 because in 3, the HFOSC is turned off)

JMP $ ; jump to current location '$'
; (endless loop)


;****************************************************************************
;
; System Interrupt Functions
;
;*****************************************************************************

;*****************************************************************************
;*
;* unused/invalid interrupt processing
;*
;*****************************************************************************
INVINT NOP
RETI


;*****************************************************************************
;*
;* Watchdog Timer interrupt processing
;*
;*****************************************************************************
WDTIRQ NOP
RETI


;*****************************************************************************
;*
;* USER NMI interrupt processing
;*
;*****************************************************************************
USERNMI NOP
RETI


;*****************************************************************************
;*
;* SYSTEM NMI interrupt processing
;*
;*****************************************************************************
SYSTEMNMI
NOP
RETI


END


Thanks,
Robert

Hi Robert,

Sorry that MSP430L092 A-POOL not support ADC, DAC available at the same time, you can refer to the A-POOL block diagram on datasheet.

regards
KC