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MSP432P401: Part locking up, upon reset holds Reset Low.

We saw the issue in which the micro was not starting.  We had powered up the device and the application firmware was running but the LEDs that were flashing suddenly stopped.  We tried re-powering and found that the MCU reset was low (~200mV).  What conditions could cause the reset line to be held low?  The code that we saw this issue on was written by our CM for the hardware and we do not have the complete source so it is “black box” as to what the code is doing.  I brought the unit back to my desk to try to reflash the unit and captured the below log.  After clicking the toggle reset button the re-flash was successful and the application is running again. 

[5/10/2017, 3:33:53 PM] [ERROR] CS_DAP_0: Error connecting to the target: (Error -1170 @ 0x0) Unable to access the DAP. Reset the device, and retry the operation. If error persists, confirm configuration, power-cycle the board, and/or try more reliable JTAG settings (e.g. lower TCLK). (Emulation package 6.0.576.0) No connection possible. This could be caused by the device having gone to low power mode and disabling JTAG PINs. You have the option to either toggle reset or try to use SWD instead.

[5/10/2017, 3:33:59 PM]

[5/10/2017, 3:33:59 PM]

[5/10/2017, 3:33:59 PM]

[5/10/2017, 3:34:00 PM] [INFO] CORTEX_M4_0: Flash Programmer: Erasing main memory

[5/10/2017, 3:34:00 PM] [INFO] CORTEX_M4_0: Flash Programmer: Writing 9448 bytes to flash memory 0x00000000

[5/10/2017, 3:34:01 PM] [SUCCESS] Program Load completed successfully.

  • Hi Blake,

    This could be related to a wrong or out of specification configuration, maybe something similar to this post. e2e.ti.com/.../574203

    Could they share us how are they setting up their clocks and vcore configurations?? Also how many devices they have seen with this issue??

    Thanks,

    David
  • Hi David,

    This is in debug so they have only seen it in a handful of proto's provided by the consultant doing the code.

    Could you email me offline and I will share the startup code. They are hyper conscious of sharing code in an open forum so we should do it offline. bcarpenter@ti.com

    We can post the results here after we isolate the problem.

    Thanks!

    Blake
  • This is was handle offline and the problem had to do with the number of flash wait cycles and the Operating CPU frequency.

    The DCO (MCLK/SMCLK) was being configured to 24MHz with LDO_VCORE0 (out of spec). “Violation of the maximum frequency limitation for a given wait-state configuration results in non-deterministic data or instruction fetches from the flash memory.”

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