MSP430FR5989: ADC12TOVIFG recovery issues

#include <msp430.h> 
#include <stdint.h>



#define _N_POINTS		1024


#pragma LOCATION(_data_0, 0x15000)
static volatile uint16_t _data_0[_N_POINTS];
#pragma LOCATION(_data_1, 0x17000)
static volatile uint16_t _data_1[_N_POINTS];

static volatile uint16_t _n_tov = 0;
static volatile uint16_t _n_ov = 0;

/* Static function declarations */
static void _startAdcCollection(void);
static void _stopAdcCollection(void);

int _system_pre_init(void)
{
    /*
     * Disable the GPIO power-on default high-impedance mode to activate
     * previously configured port settings
     */
    PM5CTL0 &= ~LOCKLPM5;

    /* Unlock all segments for Write access - note, because all variables are in FRAM, we need to do this before setting any variables */
    MPUSAM |= (MPUSEGIWE | MPUSEG3WE | MPUSEG2WE | MPUSEG1WE);

    return 1;
}
/*
 * main.c
 */
int main(void)
{
    WDTCTL = WDTPW | WDTHOLD;	// Stop watchdog timer

    /* Setup the External VRef */
    P1SEL1 |= (BIT1);
    P1SEL0 |= (BIT1);

    /* Setup Analog Channels 8 and 9 */
    P9SEL1 |= (BIT0 | BIT1);
    P9SEL0 |= (BIT0 | BIT1);

    /* Setup the external crystal */
	PJSEL1 &= ~BIT4;
	PJSEL0 |= BIT4;



    /* Configure the wait states before setting the clocks */
    FRCTL0 = FRCTLPW | NWAITS_1;

    // Clock System Setup (external 32768 crystal)
    CSCTL0_H = CSKEY >> 8;                    // Unlock CS registers
    CSCTL1 = DCOFSEL_4 | DCORSEL;            // Set DCO to 16MHz
    CSCTL2 = SELA__LFXTCLK | SELS__DCOCLK | SELM__DCOCLK; // Set SMCLK = MCLK = DCO,
    CSCTL3 = DIVA__1 | DIVS__2 | DIVM__1;     // Set all dividers
    CSCTL4 &= ~(LFXTBYPASS | LFXTOFF);                      // Ensure crystal not in bypass
    /*
     * Wait for faults to clear.  NOTE: if you don't clear the fault flag, XT1 clock will default to 37.5 KHz
     */
    do
    {
        CSCTL5 &= ~LFXTOFFG;                    // Clear XT1 fault flag
        SFRIFG1 &= ~OFIFG;
    } while (SFRIFG1&OFIFG);                   // Test oscillator fault flag
    CSCTL0_H = 0;                             // Lock CS registers

    /*
     * Setup TimerA0 as a 1 second timer.
     */
    TA0CTL = TASSEL__ACLK | TACLR;
    TA0CCTL0 = CCIE;
    TA0CCR0 = 32768;

    /*
     * Setup Timer B0.1 to feed ADC module in extended sampling mode [using extended mode to prevent having to toggle the ENC bit]
     *  The initial timer is set to run 2 channels at 150 Khz.  The timer source is 8MHz SMCLK, but 2 channels requires the PWM
     *  to trigger each channel, so need to cut the period in half.
     *  TB0.2 will trigger the DMAs to read the data.
     */
    TB0CTL = (TBSSEL__SMCLK | TBCLR);
    TB0CCTL0 = 0x0000;
    TB0CCR0 = 20; //26;           // Period = 3.26us [x2 for each channel]
    TB0CCR1 = 8;            // 8 clocks for sampling
    TB0CCTL1 = 0x0000;      // Clear the output line first to drive low
    TB0CCTL1 = OUTMOD_7;    // Set output unit to outmod 7
    TB0CCR2 = TB0CCR0 - 4; //TB0CCR1 + 16;		// Per the users guide, conversion time takes 15 clocks plus a sync
    TB0CCTL2 = 0x0000;      // Clear the output line first to drive low

    /*
     * Setup ADC Module.  ADC12CLK => SMCLK.
     */
    ADC12CTL0 = ADC12SHT1_1 | ADC12SHT0_1;        // Should not matter since we are using extended sampling mode
    ADC12CTL1 = ADC12SHS_3 | ADC12SSEL_3;         // Extended sampling mode, TimerB0.1 SAMPCON, 8MHz ADC12CLK
    ADC12CTL2 = ADC12RES_2;                       // 12-Bit
    ADC12CTL3 = 0x0000;
    /* Setup Analog channels 8 and 9 [these are channels getting sampled] */
    ADC12MCTL0 = (ADC12VRSEL_4 | ADC12INCH_8);              // External Reference
    ADC12MCTL1 = (ADC12VRSEL_4 | ADC12INCH_9 | ADC12EOS);
    ADC12IER0 = 0x0000;
    ADC12IER1 = 0x0000;
    ADC12IER2 = (ADC12TOVIE | ADC12OVIE);
    ADC12IFGR0 = ADC12IFGR1 = ADC12IFGR2 = 0x0000;

    /*
     * Setup DMA0 and DMA1 to pipe data from the ADC12 registers into the data buffers.
     * Triggered by TB0.2, not by the ADC12IFG.  It was found that the ADC12IFG cannot
     * be used to trigger BOTH DMAs.  This however means every other sample for each
     * channel is going to be garbage, but that is OK.
     */
    DMACTL0 = (DMA1TSEL_8 | DMA0TSEL_8);
    DMA0CTL = (DMADT_0 | DMADSTINCR_3 | DMASRCINCR_0);
    *((uint32_t*)&DMA0SA) = (uint32_t)&ADC12MEM0;
    *((uint32_t*)&DMA0DA) = (uint32_t)&_data_0;
//    __data20_write_long((uint32_t)&DMA0SA, (uint32_t)&ADC12MEM0);
//    __data20_write_long((uint32_t)&DMA0DA, (uint32_t)&_data_0);
    DMA1CTL = (DMADT_0 | DMADSTINCR_3 | DMASRCINCR_0 | DMAIE);
//    __data20_write_long((uint32_t)&DMA1SA, (uint32_t)&ADC12MEM1);
//    __data20_write_long((uint32_t)&DMA1DA, (uint32_t)&_data_1);
    *((uint32_t*)&DMA1SA) = (uint32_t)&ADC12MEM1;
    *((uint32_t*)&DMA1DA) = (uint32_t)&_data_1;


	/* Enable Interrupts */
	_enable_interrupts();
	_no_operation(); // Needed because the next instruction after enable is always executed due to pipelined architecture

    _startAdcCollection();
    while (1)
    {
		__bis_SR_register(LPM0_bits);
		__no_operation();
    }

	return 0;
}


static void _startAdcCollection(void)
{
	TB0CCTL0 = 0x0000;
	TB0CCTL1 = 0x0000;	// Clear the output line
	TB0CCTL1 = OUTMOD_7;
	TB0CCTL2 = 0x0000;
    TB0R = TB0CCR0 - 1;     // Start 1 tick behind CCR0 value, so that the timer is triggered high immediately

	/* Setup the DMAs */
	DMA0CTL &= ~(DMAIFG);
	DMA0SZ = _N_POINTS;		// Multiply by 2 to account for garbage
	DMA1CTL &= ~(DMAIFG);
    DMA1SZ = _N_POINTS;
    DMA0CTL |= DMAEN;
    DMA1CTL |= DMAEN;

    /* Enable the ADC Module */
    ADC12CTL1 |= ADC12CONSEQ_3;
    ADC12CTL0 |= (ADC12ENC | ADC12ON);

    /* Start the timer */
    TB0CTL |= (MC__UP);
}

static void _stopAdcCollection(void)
{
	/* Stop */
	ADC12CTL1 &= ~(ADC12CONSEQ_3);      // Reset to single channel mode
	ADC12CTL0 &= ~(ADC12ENC + ADC12ON); // Reset ENC and ON bits
	TB0CTL &= ~MC_3;                    // Stop timer

	ADC12IFGR0 = 0x0000;
	ADC12IFGR1 = 0x0000;
	ADC12IFGR2 = 0x0000;

	/* Clear the CCTL registers (to clear the output lines) */
	TB0CCTL0 = 0x0000;
	TB0CCTL1 = 0x0000;
	TB0CCTL2 = 0x0000;

	DMA0CTL &= ~(DMAEN | DMAIFG);
	DMA1CTL &= ~(DMAEN | DMAIFG);

}

#pragma vector=TIMER0_A0_VECTOR
__interrupt void timerA0_ccr0_isr(void)
{
	TA0CTL &= ~(MC_3);

	/* Start the Timer/ADC/DMA */
	_startAdcCollection();
}

#pragma vector=ADC12_VECTOR
__interrupt void adc12Isr(void)
{
	switch (__even_in_range(ADC12IV, 76))
 	{
 		case 0:
 			/* no interrupt */
 			break;
 		case 2:
 			/* MEMx Overflow error */
 			_n_ov += 1;

 			/* Simulate delay in software */
// 			__delay_cycles(160);
 			_stopAdcCollection();

 			/* Change the collection parameters to much a slower rate, to show that the overflows still occur */
 			TB0CCR0 = 488;		// 8Khz, 2 channels

			/* Delay 1 second */
			TA0CTL |= MC__UP;
 			break;
 		case 4:
 			/* Conversion Time Overflow error */
 			_n_tov += 1;

 			/* Simulate delay in software */
// 			__delay_cycles(160);
 			_stopAdcCollection();

 			/* Change the collection parameters to much a slower rate, to show that the overflows still occur */
 			TB0CCR0 = 488;		// 8Khz, 2 channels
 			TB0CCR2 = TB0CCR0 - 4;

			/* Delay 1 second */
			TA0CTL |= MC__UP;
 			break;
 		case 6:
 		case 8:
 		case 10:
 			break;
 		case 12:
 		case 14:
 		case 16:
 		case 18:
 		case 20:
 		case 22:
 		case 24:
 		case 26:
 		case 28:
 		case 30:
 		case 32:
 		case 34:
 		case 36:
 		case 38:
 		case 40:
 		case 42:
 		case 44:
 		case 46:
 		case 48:
 		case 50:
 		case 52:
 		case 54:
 		case 56:
 		case 58:
 		case 60:
 		case 62:
 		case 64:
 		case 66:
 		case 68:
 		case 70:
 		case 72:
 		case 74:
			/* ADC12MEMx Interrupt - ADC12IFGx */
 			break;
 		case 76:
			/* ADC12RDY Interrupt */
 			break;
 		default:
 			break;
 	}
}

#pragma vector=DMA_VECTOR
__interrupt void dmaIsr(void)
{
 	switch(__even_in_range(DMAIV, 16))
 	{
 		case 0:
 			break;
 		case 2:
        	/* DMA0 */
        	break;
 		case 4:
        	/* DMA1 */

 			/* Simulate delay */
// 			__delay_cycles(160);

 			_stopAdcCollection();

			/* Delay 1 second */
			TA0CTL |= MC__UP;

        	break;
 		case 6:
        	/* DMA2 */
        	break;
 		case 8:
 		case 10:
 		case 12:
 		case 14:
 		case 16:
 			break;
 		default:
 			break;
 	}
}