Part Number: MSP432P401R
I am running into errata EUSCI43 . In the first solution to the errata it says that EUSCI43 can be avoided by using a synchronous clock source. I am unsure of what that means or how to set it up. I have the following clock configuration:
MAP_CS_setDCOFrequency(CLK_FQ); // Setting DCO (clock) to the specified clock speed
MAP_CS_initClockSignal(CS_SMCLK, CS_DCOCLK_SELECT, CS_CLOCK_DIVIDER_1); // Tie SMCLK to DCO
MAP_CS_initClockSignal (CS_ACLK, CS_VLOCLK_SELECT, CS_CLOCK_DIVIDER_1); // Tie ACLK to VLO
CLK_FQ = 8000000
And I also have this in the I2C configuration:
// I2C Master Configuration Parameter
const eUSCI_I2C_MasterConfig ACCEL_i2cConfig =
{
EUSCI_B_I2C_CLOCKSOURCE_SMCLK, // SMCLK Clock Source
8000000, // SMCLK = 8MHz
EUSCI_B_I2C_SET_DATA_RATE_100KBPS, // Desired I2C Clock of 100khz
0, // No byte counter threshold
EUSCI_B_I2C_NO_AUTO_STOP // No Auto-stop
};
What is a synchronous clock source, and how would I set one up?
EUSCI43 states:
Communication stalled when polling UCBxRXIFG
\When using the USCI_B I2C module as a receiver, if an asynchronous event occurs during the read of the UCBxRXIFG interrupt flag, the flag could be unintentionally cleared. This may result in the I2C communication being stalled.
Workaround 1. If the device functions as an I2C master receiver, use synchronous clock sources for operation.
OR 2. Avoid polling UCBxRXIFG. Using the standard interrupt service routine to service the UCBxRXIFG interrupt flag significantly reduces the probability of this errata occurring. Avoid register access to UCBxCTLW0, UCBxSTATW, UCBxRXBUF, UCBxTXBUF, UCBxIFG, & UCBxIV while transmit or receive operation is ongoing and UCBxRXIFG or UCBxTXIFG is expected to be set.
OR 3. Use the clock low time-out select feature (UCCTLO.UCBxCTLW1) to enable a timeout window. In the event that the I2C communication is stalled, use the clock low time-out interrupt to reset the eUSCI module and re-initiate communication.
