This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

MSP430FR2433: Apparently defective chip. Mouser suggests I check here first.

Part Number: MSP430FR2433
Other Parts Discussed in Thread: MSP430F5529, MSP430G2412, MSP-TS430RGE24A

I got some MSP430FR2433 chips from mouser and some more from the TI e-store. Their wafer ids are 730053705 (mouser) and 730053700 (TI e-store). I've programmed the following program and it doesn't work. The same program works fine on the MSP430G2412 (if I change the target/header) and the MSP430F5529 (though I may have used different port numbers there, I don't recall). I've used both the msp430-gcc toolchain and the IAR toolchain with the same results. On the G2412 it works exactly as expected, P2.0 high, P2.1 toggles and P2.0 is low. On the FR2433 all outputs are low. Just as another wrinkle, if I use the JTAG shared pins instead (1.4-1.7) it works just fine. And yes, I've checked every single other pin on the chip (1.0-1.3, 2.0-2.7 and 3.0-3.2), they all exhibit the same behavior. Yes, I'm using proper anti-static procedure: anti-static wrist strap, anti-static mat and on the last test in the clamshell only grabbing the edges of the IC. Am I crazy, or are these parts defective?

#include <msp430fr2433.h>

int main() {
    volatile int p2in, i;
    WDTCTL = WDTPW | WDTHOLD;

    P1OUT = 0xff;
    P2OUT = 0xff;
    P2DIR = 0x03;

    while(1) {
        p2in = P2IN;

        for(i=0; i<32767; ++i) {
        }

        P2OUT ^= 0x02;
    }

    return 0;
}

P.S. I'm programming both on a custom board and with the MSP-TS430RGE24A. Some have not even touched my custom board, so that's not the problem.

  • Hi Alex!

    Your chips will be fine. The FR devices are a bit different compared to G devices, for example. Add this line

    PM5CTL0 &= ~LOCKLPM5; // Disable the GPIO power-on default high-impedance mode
                          // to activate previously configured port settings

    right after your port initialization and it should work as expected.

    Dennis

  • Ok, that works, but someone should really explain to the TI guys, that the manual makes no sense. What the manual says (below) makes it sound both as if the bit should be cleared on power up (I ignored the 1 in the reset column because I figured there was some sort of reset to 1 and then get cleared in some sort of complicated state machine on startup), and as if this should only affect the entry/exit of LPMx.5 modes which I'm not using. It says that "Pin state is held during LPMx.5 entry and exit." As far as I know I'm neither entering nor leaving any LPM modes, let alone LPMx.5, and even if I was, I'm not permanently in the state of LPMx.5 entry/exit, so it still shouldn't affect me. (I.e. I think I read that register before and just ignored it since the manual was very clear (or unclear if you like) that it applied to me).

    "Lock I/O pin and other LPMx.5 relevant (for example, RTC) configurations upon
    entry to or exit from LPMx.5. After the LOCKLPM5 bit is set, it can be cleared
    only by software or by a power cycle.
    This bit is reset by a power cycle; that is, if SVSH (if enabled) or brownout
    triggered a reset.
    0b = LPMx.5 configuration is not locked and defaults to its reset condition.
    1b = LPMx.5 configuration remains locked. Pin state is held during LPMx.5 entry
    and exit."

  • When things are not clear, having a look at the code examples for the different processors often help.

    Good to hear it works now!

    Dennis

  • A. I did look at some code samples from somewhere. I'm not sure if it was included in IAR Kickstart or just some code I saw lying around these forums, you're right that that sample code clearly has it. What I was looking at did not, and didn't work.

    B. The manual is not "confusing" it is flat out wrong. I read it and moved on, because it states that such locking occurs on entry and exit to LPMx.5 modes. I'm not entering/exiting LPMx.5 modes, so as written, that bit in that register doesn't apply to me. Just saying, someone should *really* fix that manual.

**Attention** This is a public forum