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CCS/MSP430F5172: unstable clock

Tomasz Ciesla
Intellectual 690 points

Part Number: MSP430F5172

Tool/software: Code Composer Studio

hi all,

I've changed system clock to 18 MHz using FLL (and PMMCOREV = 2). Then I've muxed the clock to pin (P3.4) and had a look at it on the oscilloscope. The FLL is configured as follows:

	UCSCTL3 |= SELREF_2;
	__bis_SR_register(SCG0);
	UCSCTL0 = 0;
	UCSCTL1 = DCORSEL_7;
	UCSCTL2 = FLLD_1 + 547;
	__bic_SR_register(SCG0);

On the scope I see that the clock is not stable, it has got a lot of "jitter". Even without executing this code, standard 1 Mhz clock has a "jitter"

I've managed to make is stable by switching off the FLL:

	__bis_SR_register(SCG0); 				// Disable the FLL control loop
	UCSCTL3 = SELREF_2;
	UCSCTL1 = DCORSEL_7 | DISMOD;			// set frequency range & disable modulator
	UCSCTL0 = DCO0 | DCO1 | DCO2 |DCO3;		// set DCO & MOD

Is it normal behavior?

  • 0
    TI__Genius 15370 points
    Hi Tomasz,

    You're most likely seeing the DCO modulation which mixes two DCO frequencies Fdco and Fdco+1 to produce an intermediate effective frequency. I suspect that without the modulation your DCO frequency isn't exactly 18MHz. Then when you turn on the modulation, the average frequency is close to 18MHz. So to answer your question, within reason this is normal behavior.

    Best regards,
    Caleb Overbay

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