RTOS/MSP432P401R: ADC accuracy on MSP432P401R Launchpad and custom application board

Sameer,
Can you comment about the differences between the boards or provide a schematic/layout of the custom board? Can you eliminate any differences related to the clock system? Are you working from a TI-Drivers example?

Regards,
Chris

Hi Chris,

We are using the example code from TI-RTOS in both cases (EVK and custom board). It is the adcsinglechannel project (see image attached below). I am not allowed to share the custom board schematic on a public forum, sorry! But i can tell u that we are giving 3.3V input to the circuit and connecting the AN0 pin (P5.5) to a DC supply and varying the input voltage to record various values. AN0 is just a floating pin in our circuit, very similar to the EVK. The only difference being, connections of VREF. See images below.

I would be curious if you see any difference between using the external reference and in the internal reference since in your application they are the same signal.   Is this an experiment that you have tried?  Specific to the analog voltage are there any other devices using this voltage?  What is the relationship between the analog and digital voltages (short, filter, open/isolated)?

Are there any filter components or passives on the signals that you are measuring that would be different from the EVK board?

Hello Chris,

* Internal reference and external reference yield same/similar results

* Analog and digital voltages are separated by a capacitive filter, please see image below

* No passives different from EVK.

Thank you Sameer. The possible sources of the differences would be the supplies, references, clocks, source impedance, and noise.

(1) Supplies/references
a. This does not appear to be the issue as there is good decoupling between AVCC and DVCC.
b. The code example is the same for both, so no delta with configuration
(2) Clocks/Source Impedance
a. The clocking for the ADC changed between SDK revisions 1_30_00_40 (TIRTOS_msp43x_2_20_00_06) and 1_40_01_00. Please confirm that you are using the latest SDK driver.
i. In version 1_30_00_40 the default power level is 2 (48Mhz MCLK) and the MCLK is used to source the ADCCLK which cannot exceed 25Mhz.
b. The sample-hold time for the ADC changed between SDK revisions 1_30_00_40 and 1_40_01_00. Please confirm that you are using the latest SDK driver.
i. In version 1_30_00_40 the sample-hold time is defined as 4ADCCLKs, at 48Mhz this means that the sample-hold time is about half of the intended time.
c. Confirm the clock frequencies are as expected (25Mhz, SYSOSC output to GPIO)
(3) Noise
a. Since you are using the example, there should be no other operations that would interfere (communication,pwm, etc).


Regards,
Chris

Hi Chris,

Me and Sameer are working together, so I will reply to your questions...

2) We are using tirtos_msp43x_2_20_00_06.
we used a driverlib example code, adc14_single_conversion_repeat and adc14_single_channel_external_reference.
we even tried changing the default clock from DCO to HFXT. Set appropriate power levels but still there was no change in the output.
Along with this, Sample hold time was set to ADC_PULSE_WIDTH_192, ADC_PULSE_WIDTH_192.

3) Noise: the program was running alone.

I believe there is an issue with the configuration of these examples as well as the 2_20_00_06 version of the tirtos drivers. Specifcially, I am seeing this configuration in the adc14_single_conversion_repeat:

/* Setting Flash wait state */
MAP_FlashCtl_setWaitState(FLASH_BANK0, 2);
MAP_FlashCtl_setWaitState(FLASH_BANK1, 2);

/* Setting DCO to 48MHz */
MAP_PCM_setPowerState(PCM_AM_LDO_VCORE1);
MAP_CS_setDCOCenteredFrequency(CS_DCO_FREQUENCY_48);

/* Enabling the FPU for floating point operation */
MAP_FPU_enableModule();
MAP_FPU_enableLazyStacking();

//![Single Sample Mode Configure]
/* Initializing ADC (MCLK/1/4) */
MAP_ADC14_enableModule();
MAP_ADC14_initModule(ADC_CLOCKSOURCE_MCLK, ADC_PREDIVIDER_1, ADC_DIVIDER_4,
0);

The recommended operation is to feed the peripheral with a clock that is less than or equal to 25Mhz and not provide a higher order clock and divide down within the peripheral. Could you try using a slower clock?

MAP_ADC14_initModule(ADC_CLOCKSOURCE_ADCOSC, ADC_PREDIVIDER_1, ADC_DIVIDER_1,
0);

Regards,
Chris