Hi,
I am using an MSP430F2232 in a project that has to sample a 4-20mA loop using the ADC channel A0. To provide accurate measurements, an external reference voltage is connected across Veref+ and Veref- (pins P2.4 and P2.3). The reference negative pin (and therefore also the uP pin Veref-) are tied to ground - i.e. VeREF- = AVss.
I have setup the ADC10 to sample the relevant channel 5 times: the first sample is discarded, the following 4 are averaged in an effort to reduce any noise that may be present. I have selected tsample as 8xMCLK with DCO of approx 1.1MHz which should provide a hold time far greater than required. The SREF setting used is SREF_6 (VR+ = VeREF+ and VR− = VREF−/ VeREF-). The reference is allowed >100us to stabilise before samples are taken.
The error I have noticed is that when the input channel is tied to ground the ADC reads +4bits (equivalent to almost 5mV). The PCB is well laid-out with good ground planes. Using a DMM shows no voltage present at the uP VeREF- pin, and applying extra links to pull the uP pin to gnd does not make any difference. Applying currents to the cct or voltages directly to the uP A0 pin appears to show a fairly constant error of +4bits across the operating range. The problem also appears on the A1 input. This problem has presented itself on both of the prototypes built so far so does not appear to be a faulty component.
I have tried adjusting various settings, and found two independant ways of improving the result:
- Select the ADC setting SREF_2 (VR+ = VeREF+ and VR− = Vss). The 4bits error is removed.
- Increase the sample time to 16 or 64 MCLK pulses. The error is reduced to approx +2 bits.
I am not sure why these changes make any difference.
- The VR- pin is connected to Vss and has been measured at Vss, extra links to Vss have made no difference so why does changing SREF have any effect?
- When no input current is applied and the pin is tied to gnd the source resistance Rs is negligible therefore the value for tsample calculated from the equation in the datasheet is <0.5us - 8MCLKs should be more than sufficient; increasing the sample time should have no effect.
I have tried disabling my voltage reference and using the internal reference against either Vss or VeREF-. This also show some error when VeREF- is used. I have tried sampling VeREF- as a source (INCH9) against internal ref 1.5V and Vss (SREF_1); this gives a reading of 0bits (as expected). I then tried sampling VeREF- as a source (INCH9) against internal ref 1.5V and VeREF- (SREF_5); this gives a reading of 2bits (not as expected).
All this leads me to question the use of VeREF- as a reference input - there appears to be something going on in the processor that causes a reading <Vss thus increasing the ADC output.
Can anyone explain what is causing this behaviour?
Is there a "preferred" configuration using the ADC (using VR- = Vss seems to give "better" results)?
Is this behaviour a quirk of the MSP430F2232 or is it also applicable to other devices?
Thanks,
Chris.