• State TI Thinks Resolved
  • Locked Locked
  • Replies 2 replies
  • Answers 1 answer
  • Subscribers 78 subscribers
  • Views 1082 views
  • Users 0 members are here
Support feedback
Options
Options
Similar topics

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

MSP430FR5739: ADC10 Questions

Lawrence Wong
Genius 14970 points
Part Number: MSP430FR5739
Other Parts Discussed in Thread: LPV521

Customer looking for more information beyond what is found in the User Guide

Specific questions:

  1. How to set the ADC clock if I want to use the device clock (not the MODOSC) which is set to 1MHz at the moment.
  2. How slow the ADC can go?
  3. The external VREF decoupling requirement is 10uF and 0.1uF – do you have any experience how critical is that value?
  4. What is the difference between the V(R+) = VEREF+ buffered and V(R-) = AVSS and the V(R+) = VEREF+ and V(R-) = AVSS?
  5. How much is the leaking on the input pin when it is in analog mode?
  6. What kind of LP filtering is recommended on the input pin? I’m driving it with a LPV521, so we need to consider what the LVP521 can drive.

  • 0
    Guru 74080 points

    Hi Lawrence!

    Lawrence Wong said:
    How to set the ADC clock if I want to use the device clock (not the MODOSC) which is set to 1MHz at the moment.

    Via the ADC10SSELx bits in the ADC10CTL1 register (bit 3 and 4).

    Lawrence Wong said:
    How slow the ADC can go?

    To stay within the specified performance, the input clock range can go from 450kHz to 5.5MHz @ 2V to 3.6V supply voltage.

    Lawrence Wong said:
    The external VREF decoupling requirement is 10uF and 0.1uF – do you have any experience how critical is that value?

    If it is recommended by the manufacturer, I would not think about changing this. At least not to lower values in this case.

    Lawrence Wong said:
    What is the difference between the V(R+) = VEREF+ buffered and V(R-) = AVSS and the V(R+) = VEREF+ and V(R-) = AVSS?

    There are no further details in the datasheet or in the user's guide - I would have expected a lower input current for the external reference input compared to the unbuffered mode. For example if your reference input is sourced by a voltage divider instead of an active reference. But I cannot find anything about it - maybe anyone else can answer this? The only thing about a buffered reference is the internal one that is available for other circuitry inside the MSP430.

    Lawrence Wong said:
    How much is the leaking on the input pin when it is in analog mode?

    There is a given input impedance of 36k maximum for the internal multiplexer.

    Lawrence Wong said:
    What kind of LP filtering is recommended on the input pin? I’m driving it with a LPV521, so we need to consider what the LVP521 can drive.

    A simple RC low pass filter might be sufficient here.

    Dennis

  • 0 in reply to Dennis Eichmann
    TI__Guru**** 208917 points
    Well answered Dennis! "VEREF+ buffered" refers to buffering the external reference voltage down to the VREF level (internal reference, 1.5/2/2.5 V) by means of the internal reference buffer. This is compared to using the full input voltage level of VEREF+ as input to the pin. You may also consult figure 16-1 of the User's Guide.

    Lawrence, please let us know if you have any follow-up questions.

    Regards,
    Ryan

**Attention** This is a public forum