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Port Interrupts only enabled for I/O is not documented.

Donald Rich38
Prodigy 20 points

While it may be assumed, and can be found in the pin schematics in the device specific datasheets, the MSP340x2xx Family User Guide does not state that port interrupts (e.g. P1IFG) are disabled when the port is not selected to be I/O. This is shown on the schematic where PxSEL2.y and PxSEL.y are ORed and the result is connected to a low enable input of the latch which is set by the Interrupt Edge Select block. I also did not find this in stated in any other documentation related to MSP430 device interrupts.

The MSP340x2xx Family User Guide states "Each PxIFGx bit is the interrupt flag for its corresponding I/O pin and is set when the selected input signal edge occurs at the pin." As stated one would expect that the interrupt flag is set even if the pin is being used by a peripheral. For example, that P1IFG1 should be set at the high to low transition at the start of a byte received by USCI0 at pin 1 of port 1 if this pin is configured to interrupt on a high-to-low transition.

  • 0
    TI__Genius 13215 points

    Hi Donald,

    Thanks for developing with MSP430 device.

    I went through the MSP340x2xx Family User Guide and found in the NOTE of section 8.2.5 telling that:

    NOTE: P1 and P2 Interrupts Are Disabled When PxSEL = 1 When any P1SELx or P2SELx bit is set, the corresponding pin's interrupt function is disabled. Therefore, signals on these pins will not generate P1 or P2 interrupts, regardless of the state of the corresponding P1IE or P2IE bit.

    I would say this NOTE means that the PxIFG will not be set when the pin is being used by a peripheral, because you need to set the PxSEL to configure the port pin to be used by peripheral. As you saw in the pin schematics in the device specific datasheets, the PxIFG will be disabled by the PxSEL signal. This is proper with the User Guide.

    In the other thoughts of myself, a Port Pin could be used as different modules such as Digital I/O or other peripherals, which can be configured by the PxSELx bit. The pin interrupt is one of the function of the Digital I/O module. So you should configure the Port Pin as a Digital I/O to let the pin interrupt function work. In other word, if you set the PxSELx, the Port Pin is not work as a Digital I/O and then you shouldn't except the pin interrupt working.

  • 0 in reply to Wei.Jetim Zhao
    Prodigy 20 points

    Thank you, but there are two issues with this response.

    First, since this is an issue of both the Function Select Registers and the Interrupts, the information should also be provided in section 8.2.7 on P1 and P2 Interrupts.

    Second, either this note or the schematics in the device datasheets (specifically for MSP430G2x53 devices) is wrong. The schematics show that the generation of PxIFG.y will be disabled if either PxSEL.y or PxSEL2.y is set (not just P1SELx but also P1SEL2x in your nomenclature). The note should read: 

    When any P1SELx, P2SELx, P1SEL2x or P2SEL2x bit is set, the corresponding pin's interrupt function is
    disabled. Therefore, signals on these pins will not generate P1 or P2 interrupts, regardless of
    the state of the corresponding P1IE or P2IE bit.

    Or the Pin Schematics should show just a connection from PxSEL.y to the EN low pin of the Q Latch which generates PxIFG.y.

    P.S. It would be nice if the pin naming conventions were the same in all documents. Not P1SELx in the Family User Guide and both P1SEL.x (e.g. Table 17, with a period) and PxSEL.y (Pin Schematics) in the datasheet.

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