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Problem with external logic-level 1Mhz clock on MSP430F4270IRGZ

tadaaki matsumoto40
Expert 1215 points
Other Parts Discussed in Thread: MSP430F4270, MSP-TS430DL48, MSP430F5529, MSP430F2002

Hi, My customer use code below and trapped in do-while loop with the bit XT1OF is set 1.
My customer check that input condition (f=1MHz,VIL,VIH) is right and output(MCLK) is OK.

Please let me know your suggestions or code sample.

SCFQCTL = SCFQ_M;
SCFI0 = 0x00;
FLL_CTL0 = XTS_FLL + XCAP0PF; // HF mode
FLL_CTL1 = 0x00;
__bic_SR_register(SCG0);
__bic_SR_register(SCG1);
__bic_SR_register(OSCOFF);
__bic_SR_register(CPUOFF);

P1DIR = 0x22; // check MCLK
P1SEL = 0x22;

do {
    FLL_CTL0 &= ~XT1OF;             // Clear OSCFault flag
    IFG1 &= ~OFIFG;                 // Clear OSCFault flag
    for(i = 0x47FF; i > 0; i--);    // Delay
} while((IFG1 & OFIFG));            // OSCFault flag still set?
 
IFG1 &= ~OFIFG;

Thank you !

  • 0
    Guru 227245 points

    tmatsu said:
    __bic_SR_register(SCG0);
    __bic_SR_register(SCG1);
    __bic_SR_register(OSCOFF);
    __bic_SR_register(CPUOFF);


    This doesn't really make much sense. If CPUOFF is set, then no CPU is running to clear it. Also, all 4 instruction sshould be combined into one. (__bic_SR_register(SCG0|SCG1|OSCOFF|CPUOFF)) which is faster and smaller.

    I don't have the 4270 datasheet at hand, but doesn't it have an XT2 too? OFIFG is set if ANY of the oscillators fail. So if XT2 isn't disabled, it will cause an OFIFG even if XT1 is running. XT1OF isn't the only OF bit to clear before you can clear OFIFG.

  • 0 in reply to Jens-Michael Gross
    Expert 1215 points

    Hi, Jens-Michael, No CPUOFF is set, it runs on Active mode and MSP430F4270 don't have XT2!

  • 0 in reply to tadaaki matsumoto40
    Guru 227245 points

    tmatsu said:
    No CPUOFF is set

    That's what I meant. It cannot be set or the CPU wouldn't be running to clear it. (I should have written 'if CPUOFF were set' I think. I'm not a native speaker)

    tmatsu said:
    MSP430F4270 don't have XT2!

    Okay. But there are XT1OF, LFOF and DCOF flags. DCOF may be set if the DCO is on lowest or highest tap (even if this is teh desired setting).
    Also, LFOF may be still set - it always is after reset and I'm not sure whether it clears itself when switching to high frequency mode.
    And as long as one of the three is set, you cannot clear OFIFG.

  • 0 in reply to Jens-Michael Gross
    Expert 1215 points

    Hi, Jens-Michael, Thank you for your reply.

     I try to close our customer's issue. So we really neet to MSP430F42x0 sample code to run on TI MSP-TS430DL48 socket module.

    I heard  that MSP430F2002 and MSP430F5529 are OK with logic-level clock input from our costemers.

    MSP430F4270 datasheet says to us to do it OK, but now, we wonder that is it really possible?

    Thank you !!

     

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