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MSP430F6736A: Connection to SD24B I+/I-

Part Number: MSP430F6736A
Other Parts Discussed in Thread: MSP430F6736

Hi everyone

I have a measurement question relating to the I+/I- pins (ie  pins 3&4) on the MSP430 that is being used in a power meter....


In the circuit above (note that this is the V+/V- inputs to the SD24B) points 3 and 4 are floating and not actually connected to the chip

The AC is 120V and voltage across 1&2=0.094V  (This was predicted and measured) and voltage across 3&4=0.094V (this was also predicted and measured)

 

 

But now in the circuit above (note that this is now the I+/I- inputs to the SD24B) points 5 and 6 are floating and NOT actually connected to the chip...

The AC between AGND & LIVE (shunt) is 120V and the Load through the shunt is: 8.60A

Voltage across 1&2=2.081mV  (This was predicted and measured)
Voltage across 3&4=4.6mv  (measured)
Voltage across 5&6=4.6mv  (measured)

And when disconnecting the Load (0A): Voltage across 5&6=4.0mv  (measured)

And, since points 5 & 6 are not connected to the MCU, there is no current path. 
So we now placed a 1K resistor across points 5 & 6 to complete a current path and we observed the following:

When Load: 0A    Voltage across 5&6=1.3mv  (measured)
When Load: 8.6A Voltage across 5&6=1.64mv  (measured)  The change compared to 0A is 26%.

And then we also replaced Capacitors C8 & C12 with 33nF (instead of the 47pF shown above) and observed the following:

When Load: 0A    Voltage across 5&6=0.44v  (measured)
When Load: 8.6A Voltage across 5&6=0.42v  (measured)  The change compared to 0A is now -4.5%.

So we can easily predict our inputs for (or rather the pd across) points 1 & 2 because the current loop is complete and the impact of the capacitors is minimal based on the given current flow.
However, this is not the case for points 5 & 6 (ie pins 3 & 4) which, it seems, are VERY sensitive to any noise.

And hence we need to know, or have a benchmark, of deliverable values to the MCU regarding Pins 3 & 4.

So NOW the questions...
In order to provide correct inputs for pins 3 & 4 (ie points 5 & 6 above) we would like to know:

  1. What does the MCU's internal circuitry do at points 5 & 6 (ie pins 3 & 4) and what impact does it have when varying the capacitance values of C8 & C12?
  2. What is the recommended circuit configuration connecting the shunt to points 5 & 6 (ie to pins 3 & 4)?
  3. In order to filter out any noise effects, what is the benchmark measurements that we should aim towards for pins 3,4 and what is the recommendation for completing the current path (so as to emulate the MCU)?

 

thanks in advance

  • Moshe,

    I do not 100% understand what your problem is but I can at least give you an answer on question #1 by pointing you to the users guide.

    The external circuitry depends how fast you want to convert as you can see in the formula above.


    The following AppsNote also gives some good recommendations how to connect the analog inputs (see page #5-#6)
    www.ti.com/.../slaa517e.pdf

    What do you mean by benchmark measurement?

  • Hi Dietmar

    Thanks for the response...my question was supposed to be very simple but i am having difficulty articulating it so please bear with me.

    Looking at my circuit above:
    I want that circuit to mimic the circuit from the shunt to Pins 3 & 4 (I+/I-). Furthermore, i want to place an equivalent impedance (at points 5 & 6) that mimics the impedance the SD24B presents to my circuit.
    Why do i want to do this you may ask? So i can experiment with various values of resistors and capacitors to try and achieve an optimal & noise resistant circuit.

    So:
    1. What would be the equivalent impedance to place there? (is that the 200K ohm mentioned in the MSP430F6736 datasheet table 5-36?)
    2. Varying the caps C8 & C12 seems to have a rather marked effect on results - does TI have suggested values other than 47pF or is 47pF considered the optimal value? 
    3. In the doc slaa517e.pdf on p6 fig5 there is a cap 'c26', is this required if one is using a shunt, and is this also TI's optimal value?
    4. What does TI suggest as further noise suppressors?
    5. At the max load across the shunt, would TI recommend that i aim to have 980mV as the differential voltage between I+ & I- or a lower value?

    thanks.

  • Hi Moshe,

    no worry about language, I'm also not a native speaker, therefore we are on the same leve!

    Thanks for the background information now I think I understand your request a bit bitter:

    So the input characteristics are specified in the datasheet as you can see below:

    Cominig to your questions:

    1. Yes this is what I would recommend you 200 kOhm typical

    2. The 47 pF are also mentioned in the reference design of the single phase Emeter so I would select these values. In the end it depends how you want to dimension you low pass or anti alias filter with respect to the frequency. I recommend to use the values mentioned in the reference design.

    3. Yes I think this is a optimal value but with relation to this specific TI design and if it is recommended there please use for your modelling. It is to stabalize input voltage during sampling and filter HF noise as far as I know.

    4. The RC circuitry should be sufficient enough, keep in mind each additional circuitry will also influence your measurement

    5. Depends on the gain you select and for this you need to align it. The Apps note talks about 920mV using gain=1 if you increase gain you have decrease your voltage swing

  • Thank you Dietmar!!

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