• State Resolved
  • Locked Locked
  • Replies 5 replies
  • Answers 1 answer
  • Subscribers 78 subscribers
  • Views 3470 views
  • Users 0 members are here
Support feedback
Options
Options
Similar topics

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

Starterware/MSP430FR6972: the question of FRAM's wait state control

Jent
Intellectual 660 points
Part Number: MSP430FR6972

Tool/software: Starterware

Hi, sir

I  set MCLK to 12MHz from DCO . From FRAM Part of msp430fr6972's user guide ,I knew "The system clock for the CPU or DMA can exceed the FRAM access and cycle time requirements. For these scenarios, a wait state generator mechanism is implemented. The Recommended Operating Conditions of the device-specific data sheet list the frequency ranges with the required wait state settings. "  The Recommend Operating Conditions is following:

I confused the "NWAITSx" means.  Do it represent  the every bit of  NWAITS[2:0], or not ?  What should be set in NWAITS[2:0], if MCLK is 12MHz?

Another question ,  From msp430fr6072's  device-specific data sheet ,the Supply Current is showed at different frequency of MCLK . I want to kow the speed of operation at  different frequency of MCLK.

Cloud I understand that the speed of 16MHz MCLK  is 16 times the speed of 1MHz MCLK ? So,  1MHz 's  current consumption is assumed to be 210 uA， 16MHz‘s current consumption is assumed to be 1845 uA. Executing the same codes , 1MHz's time consumption is 16 times 16MHz.  The 1MHz's current consumption is 210uA * 16 , and 16MHz's current consumption is 1845uA*1. Therefore, 1MHz's current consumption is large than 16MHz , when they execute same codes. Is it right ?

Best regards

Jent

  • 0
    TI__Genius 14165 points

    Jent,

    answer to question #1:
    - NWAITSx=1 means 1 wait state mean you have write 0x0010 to FRCTL0 to set NWAITS[2:0] b'001.

    answer to question #2:

    - yes at 16 MHz the DCO is running 16 times faster than at 1 MHz
    - regarding the time consumption you have to be carefully because wait states activated at 16 MHz vs. 1 MHz
    - as you can see in the table the current at 1 MHz cannot be simply multiplied by 16 for 16 MHz operation otherwise the current would be 3360 uA.
    - so yes relatively you consume less power per instruction when executing at 16 MHz

  • 0 in reply to Dietmar Walther
    Intellectual 660 points

    Hello  Dietmar,

    Thank you very much for your help . 

    So, Should I set NWAITS[2:0]b'001 , if the frequence of MCLK  is large than 8MHz ?

    About the time consumption , I should calculate the effective MCLK frequency: fMCLK,eff = fMCLK / [wait states × (1 - cache hit ratio) + 1] . For exmaple , the cache hit ratio is 75%，MCLK  is 16MHz ，the fMCLK,eff = 16 / [1 × (1 - 0.75) + 1]  = 12.8MHz.  Hence, The time comsumption of 1MHz  is 12.8 times 16MHz . Is it right ? In actual operation , what is the cahe hit ratio ? Is the cahe hit ratio  related to MCLK frenquency?

    Best regards,

    Jent

  • 0 in reply to Jent
    TI__Genius 14165 points
    Hi Jent,

    So, Should I set NWAITS[2:0]b'001 , if the frequence of MCLK is large than 8MHz ?
    -> yes

    Calculating the time consumption might be easy for a very simple LED blinking program but not for a complex program.
    It depends not on frequency but on the distribution and the strucutre of your code in FRAM.
    The users guide describes the FRAM cache in following words.

    FRAM Cache
    The FRAM controller implements a read cache to provide a speed benefit when running the CPU at higher
    speeds than the FRAM supports without wait states. The cache implemented is a 2-way associative cache
    with 4 cache lines of 64 bit size. Memory read accesses on consecutive addresses can be executed
    without wait states when they are within the same cache line.

    Means we have for lines of 64 bits. If you for example have a simple while loop which fits into these cache you have a 100 cache hit makes your program running at full speed without wait states. But with function calls and interrupts like normally used in complex code it will hard to predict.
    Again if you have predictable code scenario you can analyse and calculate it.

    So cache hit ratio has nothign to do with fequency but more how the CPU accesss different addresses of the FRAM.
    The following document shows you a code example for 0% cache hit ratio on page #6 maybe it helps you to understand this a bit better looking at the picutre.
  • 0 in reply to Dietmar Walther
    Intellectual 660 points
    Thank you Dietmar，

    Could you show me the document about the code example for 0% cache hit ratio . You might forget to add it in post .
    Many thank again for your support .

    Best regards,
    Jent
  • 0 in reply to Jent
    TI__Genius 14165 points
    Jent,

    sorry here are 2 links

    Here you can find a lot about FRAM in general
    www.ti.com/.../what-is-fram.page

    Here is the document I refered in the previous post (page #6):
    www.ti.com/.../slaa526a.pdf

**Attention** This is a public forum