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MSP430FR4133: Emulated instructions purpose in MSP430 controllers

TEMC
Intellectual 955 points
Part Number: MSP430FR4133


Recently I read about addressing modes and instruction set in MSP430 controllers....There emulated instructions are there. They do not have opcode. Then how do assemble understand the operation? Can any one please explain. In any ISA, I do see opcodes for every instruction. What Is the purpose of these emulated instructions and one more is constant generator registers are linked to these instructions. Do we really need these CGs and emulated instructions?

  • 0
    Guru 318050 points

    Section 4.3.4.1 of the User's Guide says:

    The RISC instruction set of the MSP430 has only 27 instructions. However, the constant generator allows the MSP430 assembler to support 24 additional emulated instructions. For example, the single-operand instruction:

    CLR dst

    is emulated by the double-operand instruction with the same length:

    MOV R3,dst

    where the #0 is replaced by the assembler, and R3 is used with As = 00.

    INC dst

    is replaced by:

    ADD #1,dst

    The CG registers are there because they are useful (they save quite a lot of flash space and time).

    The MOV/ADD instructions above are just as small and fast as the CLR/INC instruction would be (if they actually existed), so the emulated instructions are emulated because they are not actually needed.

  • 0 in reply to Clemens Ladisch
    Intellectual 955 points

    That's fine but when I write CLR dst instruction, how the assembler can find it is an emulated instruction because emulated instructions do not have opcodes...this is what I need...Anyone knows about this?? please explain...

  • 0 in reply to Clemens Ladisch
    Intellectual 955 points
    How does assembler knows CLR dst is an emulated instruction to MOV R3,dst..??
  • 0 in reply to TEMC
    Guru 100555 points
    The assembler is the one that implements the CLR "op-code", not the CPU. The disassembler cooperates by recognizing the pattern.

    Strictly speaking, "MOV" isn't an op-code, 0x4 is; the assembler recognizes the former, the CPU only recognizes the latter.
  • 0 in reply to TEMC
    Guru 318050 points

    The assembler's opcode table just contains two entries, one for INC and one for ADD, both mapping to the same instruction number.
    (But some emulated instructions still need special handling.)

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