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DMA interrupts

ariel
Intellectual 335 points
Other Parts Discussed in Thread: MSP430F5436A

HI,

I am doing a project on the msp430f5436a.

I am using the "user experiance" demo. In this demo Timer B activates the D/A.

The first DMA channel (channel 0 ) moves the data from the output of the D/A into flash memory.

After the D/A finishes to 'fill up' a memory bank, an interrupt is raised. I am using this interrupt to configure the activation of

the two other DMA channels (channels 1 and 2)  to implement a filter on the first memory bank.

The problem is that the first channel (channel 0 ) doesn't seem to work all the time that other two channels are working.

The result is that I have the first memory bank full of D/A samples (for example from 0x10000 to 0x18000) but the second one starts to fill up only from the middle!

(for example I have 0x18000 to 0x1a000 empty, and from  0x1a000 to 0x20000 full of samples)

does anyone know why does the DMA channel behaves this way?

thanks,

Ariel 

  • 0
    Guru 227245 points

    Do I get this right, you're writing to flash using DMA? That's a tricky thing because every write locks the complete flash for some time. You cannot do any more writes, cannot execute any code (the CPU is "jumping on place" if it is executing code from flash) and read nonsense (0x3fff) during the write time. You may not even allow any interrupts during the write, as the interrupt vector will be fetched as 0x3fff as well (jumping into the void).

    If you're doing two different DMA-caused writes to flash, the second write will interrupt the first write, preventing the value from being written properly. Which channel comes fisrs depends on the trigger source as well as the DMA priority.

    Also, if the DMA controller is triggering a DMA after the first transfer has been completed, the flash controller is still busy writing the last word. So if interrupts are enabled, the CPU will fetch '0x3fff' as the address of the DMA ISR. Which usually isn't correct. Your program is 'running wild'. You need to disable interrupts before you start writing to flash. But then you won't be noticed that the DMA transfer is complete (you'll need to do busy-waiting). Alternatively, you can copy the interrupt table into RAM (the 54xx allows this), but it requires some changes in the linker files to preserve the required space at the required addres at the end of RAM. If oyu do this, the interrupt address will be fetched properly once the DMA transfer is complete, but then the CPU will 'jump on place' at the start of the ISR until the flash write is complete.

    Another possibility is to ensure that ONLY the DMA IRQ is active and the ISR for the DMA starts at 0x3ffe. Which is difficult too.

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