CCS/MSP430F6659: I2C problem using external clk

This is probably a problem in your code. Which you have not shown.

//////there are different slaves,so we initialize in write operation/////////

write(unsigned char slave_addr ,unsigned char iocreg_addr,unsigned char iocreg_val,unsigned char opreg_addr,unsigned char opreg_val)
{
P8SEL = BIT5 | BIT6; //port selection

UCB0CTL1 |= UCSWRST; // disable USCI
UCB1CTL0 = UCMST | UCMODE_3 | UCSYNC; // master mode, synchrnoucs, I2C mode
UCB1CTL1 = UCSSEL_2 | UCSWRST; // SMCLK Selected
UCB1I2CSA = slave_addr;//Slave Address
UCB1BR0 = 50; //I2C data rate ~ 20MHZ/400K=50
UCB1BR1 = 0;
UCB1CTL1 &= ~UCSWRST; //enable USC

UCB1I2CSA = slave_addr;// Slave Address

while (UCB1CTL1 & UCTXSTT);
UCB1CTL1 |= UCTXSTT | UCTR; //Start Condition sends address of slave, Transmit Mode

while( !(UCB1IFG & UCTXIFG) );//Wait until the data has been shifted out
UCB1TXBUF = iocreg_addr; //Load address of slave i/o configure register

while( !(UCB1IFG & UCTXIFG) );//Wait until the data has been shifted out
UCB1TXBUF = iocreg_val; //Load address of slave i/o configure register value

UCB1CTL1 |= UCTXSTP; //Send stop message

UCB1I2CSA = slave_addr;

while (UCB1CTL1 & UCTXSTT);
UCB1CTL1 |= UCTXSTT | UCTR; //Start Condition sends address of slave,Transmit //Mode

while( !(UCB1IFG & UCTXIFG) );//Wait until the data has been shifted out
UCB1TXBUF =opreg_addr ; //Load address of slave output register

while( !(UCB1IFG & UCTXIFG) );//Wait until the data has been shifted out
UCB1TXBUF = opreg_val; //Load address of slave output register value

UCB1CTL1 |= UCTXSTP; //Send stop message

}

1. Can you post the UART code as well?

2. Try the following:
change : UCB0CTL1 |= UCSWRST; // disable USCI
To: UCB1CTL1 |= UCSWRST; // disable USCI

I changed the UCB1CTL1|=UCWRST but it is stuking at
while( !(UCB1IFG & UCTXIFG) );//Wait until the data has been shifted out/////stucking at this position
UCB1TXBUF = iocreg_val;

Try this:
write(unsigned char slave_addr ,unsigned char iocreg_addr,unsigned char iocreg_val,unsigned char opreg_addr,unsigned char opreg_val)
{
//init
UCB1CTL1 |= UCSWRST; // disable USCI
UCB1CTL0 = UCMST | UCMODE_3 | UCSYNC; // master mode, synchrnoucs, I2C mode
UCB1CTL1 = UCSSEL_2 | UCSWRST; // SMCLK Selected
UCB1I2CSA = slave_addr;//Slave Address
UCB1BR0 = 50; //I2C data rate ~ 20MHZ/400K=50
UCB1BR1 = 0;
P8SEL = BIT5 | BIT6; //port selection
UCB1CTL1 &= ~UCSWRST; //enable USC


//First transaction
UCB1I2CSA = slave_addr;

UCB1CTL1 |= UCTXSTT | UCTR;
while(!(UCB1CTL1 & UCTXSTT));

UCB1TXBUF = iocreg_addr;
while(!(UCB1IFG & UCTXIFG));

UCB1TXBUF = iocreg_val;
while(!(UCB1IFG & UCTXIFG));

UCB1CTL1 |= UCTXSTP; //Send stop message
while(UCB1CTL1 & UCTXSTP);// Wait until stop

//sec transaction
UCB1I2CSA = slave_addr; //set new slave add ??

UCB1CTL1 |= UCTXSTT | UCTR;
while(!(UCB1CTL1 & UCTXSTT));

UCB1TXBUF = opreg_addr;
while(!(UCB1IFG & UCTXIFG));

UCB1TXBUF = opreg_val;
while(!(UCB1IFG & UCTXIFG));

UCB1CTL1 |= UCTXSTP;
while(UCB1CTL1 & UCTXSTP);


//disable USCI
UCB1CTL1 |= UCSWRST;

}

There is a problem in start bit when slave acknowledges start bit is not clearing


UCB1I2CSA = slave_addr;

UCB1CTL1 |= UCTXSTT | UCTR;
while(!(UCB1CTL1 & UCTXSTT));

UCB1TXBUF = iocreg_addr;
while(!(UCB1IFG & UCTXIFG)); ///here UCTXSTT bit is not clearing and UCTXIFG bit is not set

UCB1TXBUF = iocreg_val;
while(!(UCB1IFG & UCTXIFG));