MSP430F5438A: Using MSP430F5438A BSL UART

Hi Ankit,

0x5C00 may be the start of main code memory but is it the address your reset vector (0xFFFE) points towards to begin operation? Please look at your binary image file and revise accordingly. It is also worth mentioning that the BSL operates at 8 MHz which is carried over when the application is started, therefore the clock system needs to be completely reset for the expected operation frequency. This is covered in the second FAQ of the BSL Scripter User's Guide (SLAU655). You could alternatively choose for the BSL to write an incorrect WDTPW value to the WDTCTL for a PUC reset or set the PMMSWBOR/POR bits in the PMMCTL0 register for a BOR/POR reset.

Regards,
Ryan

Hi Ryan,

Thanks for your reply. I have few queries based on your explanation. (Please bear with me, I am still learning this)

0x5C00 may be the start of main code memory but is it the address your reset vector (0xFFFE) points towards to begin operation? Please look at your binary image file and revise accordingly. I checked the reset vector (0xFFFE) and it does point to 0x5C00.

 It is also worth mentioning that the BSL operates at 8 MHz which is carried over when the application is started, therefore the clock system needs to be completely reset for the expected operation frequency. So you mean something like this need to be added to my code?:

void Initialize_Clock(void)
{
UCSCTL3 |= SELREF__REFOCLK;
UCSCTL4 |= SELA__REFOCLK;
// initialize Timer_B module
TB0CCTL0 = CCIE; // CCR0 interrupt enabled
TB0CCR0 = 32768;
TB0CTL = TBSSEL__ACLK + MC__UP + TBCLR; // ACLK, up mode, clear TAR
}

This is covered in the second FAQ of the BSL Scripter User's Guide (SLAU655). I am not setting any clock that means it should be using the internal reference clock and DCO with default settings to generate the clock. If BSL works at 8MHz then even though I don't provide any XT1 and XT2, BSL should be able to set 8MHz using internal reference clock and DCO (Any problems BSL will face if it's using internal reference clock and DCO?). I did read the SLAU655 but I couldn't understand how it might affect my code as in my code below I am changing the delay based on the number of times the for loop will be executed. Whatever be the clock frequency, I should still see the LED blinking if I have given enough delay if my understanding is correct. So in below code if I change the assignment of i to a bigger value, I should see the LED blinking:

int main(void) {
WDTCTL = WDTPW | WDTHOLD; // Stop watchdog timer
P1DIR |= 0x01; // Set P1.0 to output direction

for(;;) {
volatile unsigned int i; // volatile to prevent optimization

P1OUT ^= 0x01; // Toggle P1.0 using exclusive-OR

i = 10000; // SW Delay
do i--;
while(i != 0);
}

return 0;
}

You could alternatively choose for the BSL to write an incorrect WDTPW value to the WDTCTL for a PUC reset or set the PMMSWBOR/POR bits in the PMMCTL0 register for a BOR/POR reset. I understood that I need to generate a software reset but I am not able to understand how BSL will do that. Are you implying that the new code that I load through the BSL should somehow be able to do it?

 

P.S. My TI output text file

@5c00
81 00 00 5C B1 13 2A 00 0C 43 B1 13 00 00 B1 13
24 00 32 D0 10 00 FD 3F 03 43
@ffd2
12 5C 12 5C 12 5C 12 5C 12 5C 12 5C 12 5C 12 5C
12 5C 12 5C 12 5C 12 5C 12 5C 12 5C 12 5C 12 5C
12 5C 12 5C 12 5C 12 5C 12 5C 12 5C 00 5C F1 03
B2 40 80 5A 5C 01 D2 D3 04 02 D2 E3 02 02 B1 40
10 27 00 00 91 83 00 00 81 93 00 00 F6 27 FA 3F
03 43 03 43 FF 3F 03 43 1C 43 10 01
q

 

 

Thanks and Regards,

Ankit

Hi Ryan,

Thanks a lot!
After generating the PUC through WDT, the reset problem is fixed.
@015C
00 00
q

Thanks and Regards,
Ankit