MSP430FR2532: Setting baudrate 115200 for MSP430

Hi,

My system (MSP430FR2532) working perfectly for baudrate 9600. But when I change baudrate to 115200, it does not work; I check on the scope and found that the duration for 1 bit is 10us (instead of 8.6us of the correct bit for baudrate 115200). Please help to check if I am missing anything? Thank you.

#define MCLK                    (8000000L)  /* MCLK Frequency in Hz */
#define CONFIG_CI_PHYDL_UART_BAUDRATE        (115200)

#if (MCLK==8000000)
#   if (CONFIG_CI_PHYDL_UART_BAUDRATE == 9600)
#       define UCOS16_VAL   1
#       define UCBRx_VAL    52
#       define UCBRSx_VAL   0x49
#       define UCBRFx_VAL   1
#   elif (CONFIG_CI_PHYDL_UART_BAUDRATE == 57600)
#       define UCOS16_VAL   1
#       define UCBRx_VAL    8
#       define UCBRSx_VAL   0xF7
#       define UCBRFx_VAL   10
#   elif (CONFIG_CI_PHYDL_UART_BAUDRATE == 115200)
#       define UCOS16_VAL   1
#       define UCBRx_VAL    4
#       define UCBRSx_VAL   0x55
#       define UCBRFx_VAL   5
#   else
#       error "Baudrate is not supported"
#   endif
#else
#error "Frequency is not supported"
#endif

/******************************************************************************
 *
 * @brief   Initializes UART
 *
 * @return  none
 *****************************************************************************/
//inline static void clock_init(void)

void TI_MSPBoot_CI_PHYDL_Init(t_CI_Callback * CI_Callback)
{
    UCA0CTLW0 = UCSWRST | UCSSEL_2;          // USCI held in reset and use SMCLK

    //P1SEL0 &= ~(BIT4 | BIT5);                 // Enable P4[2:3] for USCI_A0 UART mode
    //P1SEL1 |= (BIT4 | BIT5);                //
    P1SEL0 |= BIT4 | BIT5;

    UCA0BR0 = (UCBRx_VAL & 0xFF);           // Set Low baudrate byte
    UCA0BR1 = (UCBRx_VAL >> 8);             // Set high baudrate byte
    UCA0MCTLW = UCOS16_VAL |                 // Set modulation values
              (UCBRSx_VAL << 1) | 
              (UCBRFx_VAL << 4) ; 
    /*UCA0BR0 = 4;                                        //UCBR = INT(N/16) = 4
    UCA0BR1 = 0;
    UCA0MCTLW |= 0x5500 + UCBRF_5 + UCOS16;*/
    
    UCA0CTLW0 &= ~UCSWRST;                   // Clear SW reset, resume operation
  
    // Initialize all callbacks
    CI_Callback_ptr = CI_Callback;
    // Init state machine
    CI_State_Machine = USCI_STATE_IDLE;
}

/******************************************************************************
 *
 * @brief   Initializes the MSP430 Clock
 *
 * @return  none
 *****************************************************************************/
//inline static void clock_init(void)

static void clock_init(void)
{
    // Configure one FRAM waitstate as required by the device datasheet for MCLK
    // operation beyond 8MHz _before_ configuring the clock system.
    /**************************************************/
    WDTCTL = WDTPW | WDTHOLD;
    //FRCTL0 = FRCTLPW | NWAITS_1;

    __bis_SR_register(SCG0);                           // disable FLL
    CSCTL3 |= SELREF__REFOCLK;                         // Set REFO as FLL reference source
    CSCTL0 = 0;                                        // clear DCO and MOD registers
    CSCTL1 &= ~(DCORSEL_7);                            // Clear DCO frequency select bits first
    CSCTL1 |= DCORSEL_3;                               // Set DCO = 8MHz
    CSCTL2 = FLLD_0 + 242;                             // DCOCLKDIV = 8MHz
    __delay_cycles(3);  
    __bic_SR_register(SCG0);                           // enable FLL
    while(CSCTL7 & (FLLUNLOCK0 | FLLUNLOCK1));         // FLL locked
    
    CSCTL4 = SELMS__DCOCLKDIV | SELA__REFOCLK;        // set default REFO(~32768Hz) as ACLK source, ACLK = 32768Hz
                                                       // default DCOCLKDIV as MCLK and SMCLK source
    PM5CTL0 &= ~LOCKLPM5;                     // Disable the GPIO power-on default high-impedance mode
                                              // to activate previously configured port settings
    
    __delay_cycles(1000);
    
}

regards,

Quang