MSP430F67791A: System Frequency issue

#include <msp430.h>

void main(void)
{
    WDTCTL = WDTPW | WDTHOLD;              // Stop WDT

    // Setup P5.3 output, P1.5 SMCLK, P1.4 MCLK, P1.2 ACLK
    P5DIR |= BIT3;                          // Set P5.3 to output direction
    P5OUT &= ~BIT3;                         // Clear P5.3
    P1DIR |= BIT2 | BIT4 | BIT5;            // ACLK, MCLK, SMCLK set out to pins
    P1SEL0 |= BIT2 | BIT4 | BIT5;            // P1.2,4,5 for debugging purposes.

    // Setup LFXT1
    UCSCTL6 &= ~(XT1OFF);                  // XT1 On
    UCSCTL6 |= XCAP_3;                     // Internal load cap

    // Loop until XT1 fault flag is cleared
    do
    {
        UCSCTL7 &= ~XT1LFOFFG;             // Clear XT1 fault flags
    } while (UCSCTL7 & XT1LFOFFG);         // Test XT1 fault flag

    // Initialize DCO to 2.45MHz
    __bis_SR_register(SCG0);               // Disable the FLL control loop
    UCSCTL0 = 0x0000;                      // Set lowest possible DCOx, MODx
    UCSCTL1 = DCORSEL_5;                   // Set RSELx for DCO = 16 MHz
    UCSCTL2 = FLLD_1 | 511;                 // Set DCO Multiplier for 16 MHz
                                           // (N + 1) * FLLRef = Fdco
                                           // (511 + 1) * 32768 = 16MHz
                                           // Set FLL Div = fDCOCLK/2
    __bic_SR_register(SCG0);               // Enable the FLL control loop

    // Worst-case settling time for the DCO when the DCO range bits have been
    // changed is n x 32 x 32 x f_MCLK / f_FLL_reference. See UCS chapter in 5xx
    // UG for optimization.
    // 32 x 32 x 16 MHz / 32,768 Hz = 524288 = MCLK cycles for DCO to settle
    __delay_cycles(524288);

    // Loop until XT1, XT2 & DCO fault flag is cleared
    do
    {
        UCSCTL7 &= ~(XT2OFFG | XT1LFOFFG | DCOFFG);
        // Clear XT2,XT1,DCO fault flags
        SFRIFG1 &= ~OFIFG;                 // Clear fault flags
    } while (SFRIFG1 & OFIFG);             // Test oscillator fault flag

    while (1)
    {
        P5OUT ^= BIT3;                      // Toggle P5.3
        __delay_cycles(60000);            // Delay
    }
}