MSP430F46187: XT2 Problem

You do not need to set OSCOFF, SCG0, and GIE. Your "for (i=5; i>0;i--);" delay may have been "optimize" out by the compiler. And it is way too short anyway. The OFIFG bit in IFG1 is not for XT2 only.

Simply wait for a msec or two. The XT2 may be stable and running fine. Route it to a port pin and examine it with a scope. Or, count it and blink a LED. Either way, you can see if it is working or not.

Hi,

Thanks for the reply. This code is provided by TI to test HF XT2. (msp430x471x7_hfxt2.c)

I expect to see square wave at P1.1/MCLK pin. But nothing.

The program stucks in the OSCFault flag loop at the beginning.

Since loop variable i is volatile, it is not optimized by compiler.

I have checked it and played with loop count, but no change.

I have also checked hf crystal pins with a scope, there is nothing just like a ground.

//******************************************************************************

//   MSP430x471xx Demo - FLL+, MCLK Configured to Operate from XT2 HF XTAL

//

//   Description: Proper selection of an external HF XTAL for MCLK is

//   demonstrated using HF XT2 OSC.  OFIFG is polled until the HF XTAL

//   is stable - only then is MCLK sourced by XT2.  MCLK is buffered on P1.1.

//   //** HF XTAL NOT INSTALLED ON FET **//  <----- What does it mean?

//

//                MSP430x471xx

//             -----------------

//         /|\|              XIN|-

//          | |                 |

//          --|RST          XOUT|-

//            |                 |

//            |                 |

//            |            XT2IN|-

//            |                 | HF XTAL (455kHz - 16MHz)

//            |           XT2OUT|-

//            |                 |

//            |                 |

//            |        P1.1/MCLK|-->MCLK = HF XTAL

//

//   K. Venkat

//   Texas Instruments Inc.

//   May 2009

//   Built with CCE Version: 3.2.0 and IAR Embedded Workbench Version: 4.11B

//******************************************************************************

#include  <msp430x471x7.h>

void main(void)

{

  volatile unsigned int i;

  WDTCTL = WDTPW+WDTHOLD;                   // Stop WDT

  _BIS_SR(OSCOFF + SCG0 + GIE);             // Disable LFXT1 xtal osc & FLL loop

  FLL_CTL1 &= ~XT2OFF;                      // Activate XT2 high freq xtal

  // Wait for xtal to stabilize

  do

  {

  IFG1 &= ~OFIFG;                           // Clear OSCFault flag

  for (i = 5; i > 0; i--);                  // Time for flag to set

  }

  while ((IFG1 & OFIFG));                   // OSCFault flag still set?

  FLL_CTL1 |= SELM1;                        // MCLK = XT2

  P1DIR |= BIT1;                            // P1.1 output direction

  P1SEL |= BIT1;                            // P1.1 option select

  while(1);

}

BasePointer said:

//** HF XTAL NOT INSTALLED ON FET **//  <----- What does it mean?

This statement means that a high-frequency crystal is not installed on our TI target boards prior to shipping. You have to populate it yourself.

If the OFIFG flag is not clearing I would suspect the crystal connections. What load caps have you placed on the board? What load cap values are required by the crystal manufacturer? If you try a different crystal do you see better results?

Hi,

We are using Raltron brand for all our crystals. I have tried Raltron HS49/U and S types, their max esr values are varying between 30ohm-60ohm for our speeds. For the load capacitance, we always choose 12.5pF crystals. So on our PCB there are two 22pF as load capacitance. we tried 4Mhz, 8Mhz and 16Mhz. All had same result. As a load capacitance, on the PCB, we tried 22pF and without any load capacitors. Still no change. In that device, TI has extended HF crystal support with 16 Mhz. In the code, I also tried all XT2S bits shown below. We also checked all connections, pcbs are clean and all connections seems comming to MCU.

FLL_CTL2.XT2S Bits

XT2 range select. These bits select the frequency range for XT2.

00 0.4 to 1-MHz crystal or resonator

01 1 to 3-MHz crystal or resonator

10 3 to 16-MHz crystal or resonator

11 Digital external 0.4 to 16-MHz clock source

Thanks.

BasePointer,

How many boards are showing this issue? Are these custom designs? Do you have a TI target board to test with as a control?

You say that XT1 works properly. When testing XT2 do you have a crystal connected to XT1 as well during these tests (or was the crystal removed during the tests)? If there is only one crystal with a frequency below 8 MHz in the system, it should be connected to LFXT1. Using only XT2 causes the LFOF fault flag to remain set, not allowing for the OFIFG to ever be cleared.

If you connect one of the 4MHz crystals to XT1 do you see proper oscillation? This can be a useful test to make sure your crystal is OK.

BasePointer said:

Since loop variable i is volatile, it is not optimized by compiler.

A common mistake.
'volatile' does not mean 'don't optimize'.
It rather means 'this variable might be read or written outside program flow by everyone who has a reference to it' (e.g. hardware register/DMA access/ISR)
But since it is a local variabnle, the compiler knows for sure that nobody but the current program scope has a reference on it (unless you call an (external) function with its reference as parameter or write its reference anywhere) and therefore the volatile keyword is void.
Makign a volatile operation inside the loop (such as NOP()) will ensure that at least this operation is executred the given number of times. The loop itsellf may still be unrolled (e.g. replaced by 5 separate NOPs) making it still faster than expected.

The OFIFG bit will only clear once all four OF bits in FLL_CTL0 are clear. Setting OSCOFF should clear XT1OF/LFOF, but there's also DCOF which is set if the DCO is set to the lowest TAPs. Since the FLL+ is active per default, it tries to adjust the DCO according to the LFXT1 frequency - which is zero without a clock crystal attached (and with OSCOFF set). Setting SCG0 disables the FLL, but if the DCO is already at the lowest tap, you won't get DCOF clear and also OFIFG won't clear.

The users guide, however, states:

If there is only one crystal with a frequency below 8 MHz in the system, it should
be connected to LFXT1. Using only XT2 causes the LFOF fault flag to remain
set, not allowing for the OFIFG to ever be cleared.

So I'm not sure whether setting OSCOFF will make the XT1 OF bits a don't care for the OFIFG bit or not.

XT2OF will automatically clear once the XT2 is running. But you don't set the XT2Sx bits in FLL_CTL2, so the XT2 is expected to be 0.4..1Mhz and won't probably never come up.