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CCS/MSP430F5528: How does stabilization checking works

Rohan Kumar
Prodigy 60 points
Part Number: MSP430F5528


Tool/software: Code Composer Studio

I was going through TDC_1000_basic_spi_readwrite 's code. In main.c to check if clock is stable the following code is used:-

  do
  {
    UCSCTL7 &= ~(XT2OFFG + XT1LFOFFG + DCOFFG);
                                            // Clear XT2,DCO fault flags
    SFRIFG1 &= ~OFIFG;                      // Clear fault flags
  }while (SFRIFG1&OFIFG);                   // Test oscillator fault flag
 

How does this code works, when already SFRIFG1&=~OFIFG is used then why the condition in while will work.

  • 0
    TI__Guru 56685 points
    Hello Rohan,

    This is a standard clock stabilization loop used by MSP430. In hard, any oscillator related fault flag is automatically asserted if a fault exists. Even if you clear said flag. If any oscillator fault flag is asserted, the OFIFG is also asserted. This loops clear the respective flags, then checks the OFIFG to see if it stays clear. If the flag stays clear, then there are no faults with the oscillators and they have started up correctly.

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