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MSP430FW423: ScanIF Test Cycle Insertion additional impulse (SIFIFG3) interrupts when changing SIFDACR6/7

Part Number: MSP430FW423


Hello,

I have problem with TCI for rotation detection using ScanIF. I use Test cycles to inject 7 additional tests of my analog signal and check if signal is in expected boundaries. To calculate digital value of signal using comparator I use simple binary search algorithm:

// [...]

if((SIFCTL2 & 0x0001) != 0)
   dac1_value += delta;
else
   dac1_value -= delta;

SIFDACR6 = dac1_value;

if((SIFCTL2 & 0x0002) != 0)
   dac2_value += delta;
else
   dac2_value -= delta;

SIFDACR7 = dac2_value;

delta >>= 1;
if(delta == 0)
{
   // end of calibration process
   // dac1_value and dac2_value are my results.
}

Unfortunately During calibration process I get additional interrupts from PSM that generates false rotation counts. If I comment out these two lines everytihng is ok:

//SIFDACR6 = dac1_value;
//SIFDACR7 = dac2_value;

Above diagram shows 7 TCI during normal operation without modification of SIFDAC6/7. DBG0 - interrupt handler from ScanIF. DGB1 End of scan interrupt handler (SIFIFG1).

Above diagram shows additional counting cycles from PSM when SIFDAC6/7 are modified during 7 test cycles. Those additional cycles are in random place, on random end of scan Interrupt (picture shows only example).
DBG2 shows handler for SIFIFG3 interrupt. DBG3 is toogled when SIFDEBUG setup to 0x0001 (check current PSM state) differs from prev. That mean that real turning is detected by PSM, not only false interrupts are generated. During whole process coils are undamped and they are in stable conditions. So no state change should be done in PSM.

I use channel 0 and 1 for normal operation and SIFDAC0/1/2/3 are setup on init to constant values and not changed during whole calibration process.

Whet am I doing wrong?

Regards Maciek

  • Hi,

    I will check with our expert for you question and reply you.
  • Hi Maciek,

    When you changed SIFDACRx register, do you check if the CPU is in an active TSM sequence? You can use SIFDEBUG registor to check the TSM status, and change the SIFDACRx registor while the CPU is NOT in an active TSM sequence.

    Best regards,

    Cash Hao

  • Hi Hao,

    I'm changing the value of SIFDACR6/7 in end of scan interrupt context. So TSM sequence should be end and TSM index reset to 0. I've added small test code to main loop and at the begining of ScanIF interrupt:

    _DINT();
    
    SIFDEBUG = 0x0001;
    int current_debug_value = SIFDEBUG;
    
    if((current_debug_value & 0x1f00) != 0)
       DBG3_ON;
    else
       DBG3_OFF;
    
    _EINT();

    _DINT and _EINT are only in main loop. And I always observe, that at the begining of ScanIF, TSM index is set to 0.

    Here:

    DBG0 - ScanIF interrupt routine.

    DBG1 - ScanIF SIFIFG1 handler (where SIFDACR6/7 might be changed. They are changed on second interrupt from test cycle.)

    DBG2 - ScanIF SIFIFG3 handler -> implulse are counted.

    DBG3 - SIFDEBUG & 0x1f00 is different than 0

    DBG6 - main loop indicator -> toogle on every execution.

    My osciloscope shows same result. I have visible coil excitation and oscilation, and then I see DBG pins from interrupt handlers. Never in same time.

    Regards Maciek

  • Hi Maciek,
    So you still changing the SIFDACR6/7 during the ScanIF routine. We have already found a bug in MSP430FR698x devices, that ScanIF may get TSM1 register corruption. You can find that in ESI2 www.ti.com/.../slaz517u.pdf. You can find the workaround for this issue.

    Do you really need to change the SIFDACR6/7 while the CPU may still in an active TSM sequence?

    Best regards,
    Cash Hao
  • Hello,

    This is weird... but this resolves my issue. I will confirm that after more tests.

    I've moved calibration procedure from 'End of scan' interrupt handler to main context. No more fake impulses.

    What is weird: I use small test for current TSM state:

    _DINT();
    SIFDEBUG = 0x0001;
    int current_debug_value = SIFDEBUG;
    
    while((current_debug_value & 0x1f00) != 0)
    {
       SIFDEBUG = 0x0001;
       current_debug_value = SIFDEBUG;
    }
    _EINT();

    And it always states 0 for first while test. Exactly same as in interrupt routine. I was sure that 'End of scan' interrupt is fired right after last TSM (SIFSTOP) cycle, so I was sure, that I made modifications of SIFDACR6/7 _NOT_ while TSM is working.

    AND!!! I use first version of ScanIF not Extended ScanIF like in ESI2 bug.

    I will post some results after more tests. I hope this is the solution.

    Regards

    Maciek

  • Hi Maciek,

    The way you  writing to the SIFDEBUG register is not correct. It is described in the User Guide Page 912 

    That's way you are getting 0 all the way.

    Best regards,

    Cash Hao

  • Hi,

    I'm sure that I use mov instruction to write to SIFDEBUG. This is generated assembler:

    	.dwpsn	file "../main.c",line 629,column 4,is_stmt,isa 0
            DINT
            NOP      ; [] |629| 
    	.dwpsn	file "../main.c",line 631,column 4,is_stmt,isa 0
            MOV.W     #1,&SIFDEBUG+0        ; [] |631| 
    	.dwpsn	file "../main.c",line 633,column 28,is_stmt,isa 0
            MOV.W     &SIFDEBUG+0,r15       ; [] |633| 

    Unfortunately I was happy too fast... I still get the fake interrupts from impulse counter. Still digging what is wrong.

    =========== EDIT ===========

    I've changed the

    SIFDEBUG = 0x0001;

    to 

    asm("\t\tMOV.B #1,&SIFDEBUG+0");

    and result is same. Every time the ((SIFDEBUG & 0x1f00) == 0) == true.

    Regards

    Maciek

  • After some tests I'm sure that something is wrong.

    Alredy done:

    - I'm changing SIFDACR6/7 in main context right after "end of scan" interrupt handler.

    - I'm checking SIFDEBUG for TSM inactive state using only MOV.B to setup SIFDEBUG to 0x0001

    What is wrong? When I'm changing SIFDACR6/7 histeresis in SIFDAC0-1 and SIFDAC2-3 doesn't work correctly causing additional false impulse counting.

    At application initialization I have setup static values for SIFDAC0/1/2/3

    SIFDACR0 = 715;
    SIFDACR1 = 705;
    SIFDACR2 = 715;
    SIFDACR3 = 705;

    Previously I had 725-715 for DAC and undamped signal from my coils equals 725-727 so should be on top of hysteresis level. That's why I've changed levels to 715-705 to be further from hysteresis thresholds.

    Now!!! I'm executing two tests. Code base is identical. For first test I leave SIFDACR6/7 unmodified, for second one I'm changing values of those register using simple binary search algorithm to find current signal level from coils.

    During first test my coils are undamped and I put metal ring closer and closer to coils. I can't observe any false impulses.

    During second test my coils are undamped and I put metal ring closer and closer to coils. I can observe output from my calibration routine. At the moment, when signal from both coils is below top hysteresis level (715) but still above low hysteresis level (705), I observe false impulses (lots of them).

    Red and Blue signals are results from calibration procedure (those 7 TCI's visible on previous posts)

    Yellow are moments, where false impulse where detected. ScanIF is configured to output impulses MOD 4 so full rotation in extended state machine (PSM) have to be present.

    To be sure I have also performed same test for inversed hysteresis thresholds:

    SIFDACR1 = 715;
    SIFDACR0 = 705;
    SIFDACR3 = 715;
    SIFDACR2 = 705;

    Observation is similar. False counts are visible when signal is between hysteresis thresholds, but there are much more of them. In above example I hot 5 false impulses. When thresholds are inversed I can count about 55 false impulses in same time period.

    I'm changing software that was working on above 50000 devices for 1.5 years without any false counts. What differs now is this TCI autocalibration procedure that modifies SIFDAC6/7 registers  and mess up hysteresis completly. Currently I'm trying to generate minimal not working example. But I will not be able to post it here (public).

    Regards

    Maciek

  • Hi Maciek,

    Thanks for these tests. 

    I will keep working on this issue. If you think E2E is not a good place to share, we can talk through email. My email is cash-hao@ti.com 

    Best regards,

    Cash Hao

  • Hi,

    I want to resolve issue and share solution, but I can't share code. I'm still working on it.
    It looks like result from test cycle is taken to decide which hysteresis threshold (hi or low) is used by comparator in normal cycle. I have some tests in mind but will be at office in about couple of hours so I will test then.

    What I'm going to do, is to setup SIFDACR6/7 to constant values pattern for test cycles, to generate impulse. By knowing which comparator threshold is used for normal cycles, I theoretically can generate specific amount of false cycles. This will prove or reject my observations.

    Thanks
    Maciek.
  • Hi,

    First state of my TSM was not set to 0x0000. This was the issue. After adding "SIFTSM0 = 0x0000;" there are no more false counts and calibration works perfectly.

    Thanks for help.

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