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msp432p401y: Understanding the baudrate calculation

Marc Singer98
Prodigy 240 points
Part Number: msp432p401y


The MSP432p manual, on page 915, explains how to take a reference clock frequency and baudrate target and compute the baudrate register values.

To verify that I understand the instructions correct, I figured I would work through the table in the uartecho's hardware setup to make sure I get the same values.

For the 115200 baud config at 12MHz, I would expect the following:

 {
        .outputBaudrate = 115200,
        .inputClockFreq = 12000000,
        .prescalar = 6,
        .hwRegUCBRFx = 8,
        .hwRegUCBRSx = 0x11, // 17
        .oversampling = 1
    },

The Sx field, per the documentation, is a lookup in table 24-4 for the remainder of F/baud which is 0.1666 in this case.

What is odd is the value in the uart echo sample for Sx is 32.  At a 24MHz reference clock, I would expect that the Sx value would be 0x49, but the sample code uses 37.

Can you help me see where I'm misunderstanding the baudrate configuration computation?

Cheers

  • 0
    Prodigy 240 points
    As a follow-up, I'd like to work-out the configuration necessary for 921600 baud. When I follow the manual instructions, I get these entries:

    {921600, 24000000, 1, 10, 0xb5, 1},
    {921600, 12000000, 0, 13, 0, 0},

    I've setup the firmware to force power-level 3 which means SMCLK is 24MHz. I verified this with a call to fetch the clock frequencies.

    The entry for 921600 baud is giving me something closer to 893000 baud. My measurement is a take-off from an o-scope so it isn't precise. Still, it's pretty far from the target of 921600.

    Am I missing something?

    Cheers
  • 0 in reply to Marc Singer98
    TI__Mastermind 25045 points
    Hello,

    Interesting, this might be caused by the DCO tolerance. Which version of the SDK are you using?? At the same time let me run a couple of tests and I'll get back to you.

    Thanks,

    David
  • 0 in reply to DavidL
    Prodigy 240 points
    simplelink_msp432p4_sdk_1_60_00_12
  • 0
    TI__Mastermind 25045 points

    Hi Marc,

      The baudrate dividers were determined by using the MSP432 baudrate calculator:

    software-dl.ti.com/.../index.html

    And the UCBRSx value is 32 (0x20) because of the lookup table in the calculator.

    N 104.1667

    For this case the fractional part of N is 0.1667 and 0.1667 is less than 0.1670 and greater than 0.1430 so UBRSx = 0x20.

    Marc Singer98 said:
    At a 24MHz reference clock, I would expect that the Sx value would be 0x49, but the sample code uses 37.

    It is the same for this case, at 24MHz:

    N 208.3333

    The fractional part of N is 0.3333 and 0.3333is less than 0.3335 and greater than 0.3000 so UBRSx = 0x25.

      Hopefully this helps.

        David

  • 0 in reply to Marc Singer98
    TI__Mastermind 25045 points

    Hi Marc,

     For 921600 and 24MHz I get:

        {921600, 24000000,  1,  10,  0, 1},

    Not sure how did you get the 0xB5??

    N 26.04166667

    The fractional part of N is 0.04166667 therefore UBRSx = 0. Could you please give this a try and let me know if your target is closer to 921600.

       Best regards,

         David

  • 0
    Prodigy 240 points
    I see now that the part I was misunderstanding is that the computation of the Sx value involves rounding down to the next smallest value in the tables instead of the closest value. Thus, 0.1666 rounds down to 0.1430 instead of up to 0.1670.

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