msp430fr2311: Speeding up eUSCI SPI

Blake,

As Bruce suggested you could speed up SPI transfer a bit by getting rid of interrupts at a certain point, but that is also dependent on your MCLK speed versus SMCLK as well. I also think this maybe the issue here though. What speed are you running the MSP430 versus the SPI (SMCLK I'm assuming)?

Hi Jace,

SMCLK is running at 16mhz... I have played with UCA0BR0 between 0 and 4 as well... all seem to work. See any issue with my config?


//-------------------------------------------------------
// SPI Setup Routines
//-------------------------------------------------------
UCA0CTLW0 |= UCSWRST; // **Put state machine in reset**
// 4-pin, 8-bit SPI master

UCA0CTLW0 |= UCMST|UCSYNC|UCCKPL|UCMSB|UCMODE_1|UCSTEM; // Clock polarity high, MSB
UCA0CTLW0 |= UCSSEL__SMCLK;
UCA0BR0 = 0x4;
UCA0BR1 = 0; //
UCA0MCTLW = 0; // No modulation
UCA0CTLW0 &= ~UCSWRST; // **Initialize USCI state machine**
UCA0IE |= UCRXIE; // Enable USCI_A0 RX interrupt

Blake,

What's MCLK at? I can see some delay due to CPU if its not maxed out in this situation.

Here is what I am doing for clock config... does this set my SCLK to 16mhz as well or do I need to do something else to configure it...

//-------------------------------------------------
// Setup Clocks to 16mhz
//-------------------------------------------------

// Configure one FRAM waitstate as required by the device datasheet for MCLK
// operation beyond 8MHz _before_ configuring the clock system.

FRCTL0 = FRCTLPW | NWAITS_1;

__bis_SR_register(SCG0); // disable FLL
CSCTL3 |= SELREF__REFOCLK; // Set REFO as FLL reference source
CSCTL0 = 0; // clear DCO and MOD registers
CSCTL1 &= ~(DCORSEL_7); // Clear DCO frequency select bits first
CSCTL1 |= DCORSEL_5; // Set DCO = 16MHz
CSCTL2 = FLLD_0 + 487; // DCOCLKDIV = 16MHz
__delay_cycles(3);
__bic_SR_register(SCG0); // enable FLL
while(CSCTL7 & (FLLUNLOCK0 | FLLUNLOCK1)); // FLL locked

CSCTL4 = SELMS__DCOCLKDIV | SELA__REFOCLK; // set default REFO(~32768Hz) as ACLK source, ACLK = 32768Hz
// default DCOCLKDIV as MCLK and SMCLK source

I got the 4MHz from your scope trace, so combined with BR=4 that suggests that SMCLK really is at 16MHz.

Balke,

Yep, seems both your MCLK and SMCLK are at 16 MHz. This is fine, but it would seem indicative of your interrupts getting in the way at those speeds.

Cool... I wrote some new code on the ride back from Dallas.  I'm itching to try it out.   Huge speedup potential if all goes as expected.

Thanks to all for the help.

Blake