Open Collector On SPI-BI-WIRE Reset

 Looking at the current limits for the MSP430F16x data sheet and the debug tool schematic, the tool doesn't want to sink more than 6mA.  I added a 74LVC1G125 to tristate the reset if there is power on the debug connector.

You could always modify the circuit such that the SBW reset input coming from the debug header goes into the cathode of a small signal diode such as a 1N914 or some SMT version or a similar Schottky version and the anode of that diode is what connects to the SBW circuits on your target board, effectively converting the SBW debugger's reset signal to an OC signal once it comes into your board.  It could sink current by pulling RST low, but not source a HIGH current which could conflict with any already existing LOW driven RST state from your own circuitry.  Or of course a single gate SMT logic chip or PNP BJT + resistor could be used as an TTL push pull to OC converter too. Or just adding a 2K series resistor in series with the SBW FET would protect it, and it should still be able to drive RST LOW against a weak on-target pull-up resistor of tens of K-Ohms or more.

It is the sort of thing that is "probably" not going to cause a problem since you'd typically not have RST driven low against the HIGH drive of an external SBW debugger often or for long periods of time, and it'd be not so much worse than connecting the SBW debugger to a target that has its Vcc unpowered due to not using SBW Tool Vcc for target power at which point an external HIGH RESET  input would be clamped to GND anyway by the unpowered target.  But anyway it is best to have only OC drivers sharing an OC circuit just for functional reliability's sake even if you're not worried about the drivers being overloaded due to transient conflicts during debugging, so maybe you could change it to protect against the situation.

I worry more about plugging / unplugging the FET when the target is powered, or what the FET does if the target is unpowered or power cycled while the FET is connected since my particular board of interest at the moment is not FET tool powered.

The Schottky idea should work. Just need to limit the capacitance on the line and maybe lower the pull-up to get the rise time fast enough.  The low needs to be below 0.75v.

Thanks