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MSP430G2553: Resetting via DTR line of CP2102 USB adapter

George Hug
Genius 4350 points
Part Number: MSP430G2553
Other Parts Discussed in Thread: SN74AUP1G34

I posted about this almost a year ago:

https://e2e.ti.com/support/microcontrollers/msp430/f/166/t/585032

but wanted to revisit it to see if my solution is ok.

To briefly recap, I want to embed a CP2102 USB-to Serial adapter in an MSP430G2553 circuit so firmware updates can be performed with only a USB cable and the right software.  I won't be using the special signalling pattern on Test and /Reset to enter BSL, but need to use DTR to reset the processor from the PC software.  The problem is that the CP2102 sinks current at all its I/O pins when it is powered down, and it would always be powered down unless it is powered up from a connected USB cable.  So if I connect DTR to the  processor's /Reset pin, that pin would be clamped low, which is no good.  I asked earlier about using a capacitor in series, but was concerned about what would happen when DTR goes back high - in theory there would be a 6.6V spike at the /Reset pin.

I've ended up with this circuit:

The capacitor is the standard 2.2nF value that is supposed to still allow SBW JTAG flashing, except that it's connected to DTR, which is effectvely at ground when the CP2102 is powered down.  The 2.2K resistor is there to limit protection diode current to less than 2 mA, as specified in the datasheet, when DTR goes high.

This appears to work ok.  The negative-going reset pulse when DTR goes low goes almost to ground, and stays under 2V for almost 100 uSec.

I just wanted to be sure I haven't overlooked anything.  If anyone sees a problem, please post.

By the way, the solution suggested in the original thread of using a single gate non-inverting buffer would also work.  The SN74AUP1G34 seems to be the best choice for that.

  • 0
    TI__Genius 12315 points
    Hi George,

    Do you observe the pulse of RESET pin during disconnecting the USB cable? You need know whether it will cause a reset. And using a single gate non-inverting buffer is a good solution for these kind of questions.

    Best Regards,
    Winter Yu
  • 0 in reply to Winter Yu
    Genius 4350 points
    I don't think it's possible to predict what will happen when the USB cable is disconnected. When that happens, the DTR line will go low as the CP2102 shuts down. But that may take some time depending on how much capacitance is supporting the 3.3V rail, and that will depend on the hardware. If it's slow enough, the 47K resistor may provide enough current to keep /Reset high enough, but I think one would have to assume that a reset may well take place.

    I agree that the single-gate buffer is a good solution. But I suppose in theory a reset pulse could also result from disconnecting the USB cable if DTR goes low before the 3.3V line does. So I guess the bottom line is that if avoiding that reset is important, you would have to test the particular design and prove it one way or the other. It might be possible to power the buffer from another output line instead of the 3.3V rail, one that could be brought low in software from the PC side immediately after the reset pulse has been sent. Perhaps RTS.

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