Hi,
What is the least count of timer a in msp430f5528?
This thread has been locked.
If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.
It depends on the clock source to the timer. If the clock source is 32768Hz, then the minimum time is (1 / 32768) ~30.5us. If your clock source is 24MHz, then it is ~42ns.
Hi,
Thanks for your help. I want to use the 24 MHz crystal connected to XT2 so that I can get 42 ns accuracy. In User's manual it is written taht "After a PUC, the UCS module default configuration is: DCOCLKDIV is selected for SMCLK" . It means I have to set it XT2 Oscillator for SMCLK in my application. In other section it is written that XT2 clock can be selected for SMCLK by selecting SELS bits of UCSCTL4 and in active mode through LPM1. How to set it can you please explain.
Thanks
Pabel
Hi Pabel,
Sorry I missed your previous post.
Yes, you will have to explicitly set the source for SMCLK as XT2.
SMCLK is enabled only when operating in Active Mode, LPM0, and LPM1. It is otherwise disabled and setting it for other modes is mute.
So, to use the XT2, just set UCSCTL4 bits to all refer to XT2 as the source for MCLK and SMCLK. This will make the CPU and modules run at 24MHz.
To set the timer source, use its control register to source the clock from SMCLK (See section 17.3.1 of the manual referenced in my previous post).
**Attention** This is a public forum