Part Number: MSP430FR5739
Hi there,
Occasionally my MSP430FR5739 seems to miss a falling edge interrupt on P1.4.
Is there any errata covering the cause of this and any mitigating factors?
It causes a lot of trouble as P1.4 is being used to bit bang in this situation and timing is sensitive.
To the far right hand side you will notice the _TP4 line never is set high when Channel 06 receives its second to last falling edge.
The PORT1_VECTOR's first instruction is to set the output bit to 1 for P1OUT[3] (_TP4). It's last instruction is to clear it. It has no mechanism to return from the ISR early. Therefore _TP4 indicates the duration of the PORT1_VECTOR. High means inside the vector, low means outside of it.
P1IE[4] is set high once and never accessed again.
P1IES[4] is also set high once and never accessed again.
The selection bits are set once, and never unset or modified. The direction bits, are set once and never unset or modified. REN is never set, and OUT is never set for the associated bit in the respective registers.
Channel 06 is the line connected to P1.4 and is pulled-up. When the MSP430 pulls this down, it approaches 0.3V which you may be able to see on the analogue (bottom) line, the master device pulls it to zero.
So what's going on? Is there something causing the chip to miss the interrupt? It is kind of vital. Is there some probability an interrupt will be missed?
Voltages are 0.00-4.00V on the Channel 06 port (P1.4) as an input and the other line (_TP4) is associated with PJ.3 as an output and physically only connected to the probe.