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MSP430F5659: Vcore capacitor value

Jan Gvozdjak
Prodigy 100 points

Part Number: MSP430F5659

I have MSP430F5659 running at 16MHz with PMM_CORE_2. Both SVSL and SVML are turned on, because we need fast wake up from LPM3. 

On one device we observe random reset from SVSL.

Then  I tested PMM_CORE_LEVEL 3 and checked VCORE with oscilloscope. There was some drop in voltage. I think it was the reason for SVSL reset. Time duration was about 12us, so I added 10uF in parallel to 470nF capacitor. And now it seems to be working correctly.

My question is: in datasheet you have stated typical value of 470nF for VCORE. Can we increase it to 10uF? We do not observe now a problem on actual device. But can we make this change in production? Please, advice what can be influenced by this rapid increase in capacitor.

Thank you. Jano

  • 0
    TI__Genius 10860 points

    Hi Jano,

    I think the issue you see is linked to PMM20 bug described in the MSP430F5659 Device Errata sheet.

    Could you please check if the recommended workaround would work for your application (instead of the additional parallel capacitor)?

    Best regards,

    Britta

  • 0
    Prodigy 100 points
    Yes, it is PMM20 hw bug from Errata. I know. Just I wanted to know if we can increase capacitor on Vcore. I can not use recommended workaround - switch to normal operation (slow wake up), because processor goes to LPM3 whenever possible and we need to have live communication on serial port at 115200bps. And it needs fast wake up. Somewhere I saw that Cvcore should be at least 10 times lower ten capacitor on power supply to processor. We can do it. Why in datasheet there is only one recommended 470nF value?

    Jano
  • 0 in reply to Jan Gvozdjak
    TI__Genius 10860 points
    Hi Jano,

    we don't recommend to increase the capacitor on Vcore as this might lead to other problems if the sleep time is too short for the internal resistor to discharge the capacitances. The internal resistor is obviously designed for an external cap as referenced in the datasheet (470nF). It may lead to unexpected behaviour as the LDO wouldn't start up from the expected voltage level. Besides, a higher cap value can enable increased peak current values which can potentially cause damage.

    You could try to disable SVML and SVSL when going into LPM3 and enabling them again after fast wake-up (just make sure that enough time passed so that the Vcore dip has already passed).

    Best regards,
    Britta
  • 0 in reply to Britta Ruelander
    Prodigy 100 points
    Dear Britta,

    I will test your proposed solution, but it will take few days... I will let you know the results.

    Jano
  • 0 in reply to Jan Gvozdjak
    TI__Genius 10860 points
    Hi Jano,

    yes, please let me know if this works for you (and if so, please click the "Verify answer" button).
    If not we'll go ahead to tackle this problem statement.

    Best regards,
    Britta
  • 0 in reply to Jan Gvozdjak
    TI__Genius 10860 points
    Hi Jano,

    any update on the current status? Did you have time to test the proposed solution?

    Best regards,
    Britta
  • 0 in reply to Britta Ruelander
    Prodigy 100 points

    Dear Britta, not yet. Please, give me a day or two. I will keep you informed. It is not a 5 minutes task, because I have to find all places where MPS goes to LPM3 and then where it wakes up. But I will test that certainly. 

    Jano

  • 0 in reply to Jan Gvozdjak
    TI__Genius 10860 points
    Hi Jano,

    any updates yet?
    Please let me also know if I can close this thread in case the application is working.

    Best regards,
    Britta
  • 0 in reply to Britta Ruelander
    Prodigy 100 points

    Dear Britta,

    I am trying to reproduce the problem - but now it disappeared. We did not made any changes in HW. Just SW was altered... Now, my setting is PMM_CORE_LEVEL_2 and both SVSL and SVML are enabled. It works fine. 

    It seems it is really occasionally appearing problem. I will make further tests (with developing other part of the software) and if it will appear again, I will test your suggestion. So, for now thank you for support. 

    Yours Sincerely

    Jano

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